As technology nodes shrink below 90 nm, high static power consumption has become one of the biggest problems of CMOS based circuits due to the exponential leakage current of transistors. Spintronic devices such as magnetic tunnel junction (MTJ) due to their fascinating More
As technology nodes shrink below 90 nm, high static power consumption has become one of the biggest problems of CMOS based circuits due to the exponential leakage current of transistors. Spintronic devices such as magnetic tunnel junction (MTJ) due to their fascinating features such as low static power consumption, non-volatility, high endurance, compatibility with CMOS transistors and high-density fabrication are one of the promising candidate for designing hybrid MTJ/CMOS circuits and overcoming high static power consumption of CMOS based circuits. In this paper, a fully nonvolatile and low power hybrid MTJ/CMOS full-adder circuit for Realization of Process in Memory is proposed. The simulation results show that all the proposed circuit is at least 50% faster than all previous counterparts, the power output delay is 39% lower than the previous design, and does not impose high hardware overhead.
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