In this work, novel gallium-nitride (GaN) high electron mobility transistor (HEMT) with a p-layer in the barrier at source and drain sides (SD-PL) is reported. Important parameters such as gate-source and gate-drain capacitances, maximum DC trans-conductance (gm), cut o
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In this work, novel gallium-nitride (GaN) high electron mobility transistor (HEMT) with a p-layer in the barrier at source and drain sides (SD-PL) is reported. Important parameters such as gate-source and gate-drain capacitances, maximum DC trans-conductance (gm), cut off frequency (fT), maximum lateral electric field, breakdown voltage, DC output conductance (go) and saturated drain current of the proposed structure are studied in details using two-dimensional and two-carrier device simulations. The simulation results of the proposed structure are compared with those of the source side p-layer in the barrier (S-PL), drain side p-layer in the barrier (D-PL) and conventional structures. According to the extracted results, the proposed structure improves the gate-source capacitance, maximum gm, cut off frequency and go compared to the D-PL structure. Also this new structure reduces the peak electric field at the gate corner near the drain and consequently increases the breakdown voltage significantly in comparison with the conventional structure. Increasing p-layer length (LP) and thickness (TP) in the SD-PL and S-PL structures, improves the breakdown voltage, gate-source capacitance, gate-drain capacitance and go.
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