Nowadays, analog to digital (A/D) converters are indistinguishable parts of system on chip (soC) structures because they omit the distance between analog real data and digital logic world. Due to this fact and ever increasing trend for using portable instruments, the fi More
Nowadays, analog to digital (A/D) converters are indistinguishable parts of system on chip (soC) structures because they omit the distance between analog real data and digital logic world. Due to this fact and ever increasing trend for using portable instruments, the figures of merit for design of these converters such as speed, power and occupied area are improved. Different methods are proposed to improve the performance of these converters. In this paper, we design a fast and low power ADC using carbon nano-tube field effect transistor (CNTFET) and then its performance is comprehensively compared with a MOSFET based counterpart at the same technology node. The performance is studied two encoders: ROM and Fat tree. The obtained results are presented using HSPICE simulator at 0.9 V power supply. The simulated data from CNTFET based converter shows significant improvements in delay and power compared with its CMOS based counterpart. The power and delay obtained from CNTFET based converter using ROM encoder are improved by 92.5% and 54% with respect to the same parameters obtained from CMOS based design while the improvements using a Fat tree encoder in CNTFET converter reaches 93% and 72% in comparison with CMOS conventional design.
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Designers of modern digital and analog systems have been using multiple voltage levels in one circuit to increase performance. To convert voltage levels in high-performance circuits, it is necessary to use voltage level shifter (LS) circuits with high speed and low powe More
Designers of modern digital and analog systems have been using multiple voltage levels in one circuit to increase performance. To convert voltage levels in high-performance circuits, it is necessary to use voltage level shifter (LS) circuits with high speed and low power consumption. In this article, a high-performance LS circuit called LSBB (Level Shifter based on Body Biasing) is presented. LSBB consists of three parts: body biasing, current mirror circuit, and pull-up and pull-down circuit. The main idea of this design is to use the biasing circuit to depend on the base of the body of the transistors of the input stages to the VDDL voltage. This dependence leads to changes in the threshold voltage and as a result changes in the delay and power consumption to increase the performance of the circuit. Implementation in 180 nm TSMC technology and simulation with VDDL equal to 0.4 V, VDDH equal to 1.8 V and input frequency 1 MHz indicates the correct operation and high-performance of the proposed circuit, the delay values are 21.9 nS, the power consumption is 129 nW and the PDP equal to 2825 nW*nS confirms the high-performance of LSBB.
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