In this paper a 5th-Order single-loop Sigma-Delta Modulator with low distortion structure is presented. This structure, which uses integrator and IIR filter concurrently, has relatively less feedforward paths and modulator coefficients. Thus, its sensitivity to coeffici More
In this paper a 5th-Order single-loop Sigma-Delta Modulator with low distortion structure is presented. This structure, which uses integrator and IIR filter concurrently, has relatively less feedforward paths and modulator coefficients. Thus, its sensitivity to coefficient mismatching is reduced. To lower the power consumption of the modulator, the 2-order IIR filter block is implemented by single OTA, and a passive adder is used to realize input quantizer adder. Simulation results show that this structure can achieve 15-bit of resolution and 6 MHz input signal bandwidth, with 1.2 V supply voltage using a 0.13 µm CMOS technology. Power consumption of modulator is 53 mW. Comparing with other structures, the proposed modulator has higher performance because of increasing the DR and input bandwidth of modulator without extra increasing the power consumption.
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