One of the popular methods in design for testability (DFT) is scan design which leads on increase observability and controllability in circuit nodes. In this paper, we present a scan cell design which decreases the number of transistors, improves PDP and decreases energ More
One of the popular methods in design for testability (DFT) is scan design which leads on increase observability and controllability in circuit nodes. In this paper, we present a scan cell design which decreases the number of transistors, improves PDP and decreases energy usage. The first proposed design is an optimized version of integrated low power gating scan cell, and the main idea of this design is reducing leakage current in the part of the circuit which is not used. Also, this design has the ability of reducing the propagation delay due to decreasing output parasitic capacitance. In the second proposed design, the scan cell is designed for controlling in pull down part of the inverter at slave latch so that static power consumption is diminished when current path is cut in unnecessary position. Simulations are carried out in 22 nm PTM technology CMOS by Hspice software. The results show that the proposed designs are superior to the previous designs considering propagation delay which is decreased, and enhanced static power consumption.
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