شبکه بر تراشه با ولتاژ تطبیقی چندسطحی برای مدیریت حافظه توان آگاه در پردازنده‌های چندهسته‌ای
محورهای موضوعی : مهندسی برق و کامپیوترسیده معصومه مومنی 1 , هادی شهریار شاه حسینی 2 *
1 - دانشکده مهندسی برق، دانشگاه علم و صنعت ایران، تهران، ایران،
2 - دانشکده مهندسی برق، دانشگاه علم و صنعت ایران، تهران، ایران
کلید واژه: چندپردازنده, سامانه بر تراشه, مدیریت انتقال داده‌ها, حافظه نهان, مدیریت انرژی.,
چکیده مقاله :
مقیاس‌بندی ولتاژ، یک روش پرکاربرد برای کاهش مصرف انرژی است که هزینه آن، افزایش تأخیر در شبکه در سامانه‌های بر تراشه چندپردازنده‌ای است. برای کاهش این هزینه عملکردی بر شبکه و سیستم، کاهش میزان جابه‌جایی داده‌ها و ارتباط‌ها در شبکه باید مورد توجه قرار گیرد. در برنامه‌های کاربردی حافظه‌محور و ارتباط‌محور، بخش قابل توجهی از تأخیر شبکه به دلیل ترافیک ناشی از عدم دسترسی به حافظه نهان است. در این مقاله از روش مقیاس‌بندی ولتاژ به صورت تطبیقی و چندسطحی استفاده می‌کنیم؛ در حالی که از فضای خالی حافظه میانگیرهای ورودی در گره‌های شبکه بر تراشه برای کاهش ترافیک ناشی از عدم دسترسی به حافظه نهان استفاده می‌شود. بنابراین روش پیشنهادی باعث افزایش کارایی حافظه و کاهش مصرف انرژی تراشه می‌شود. به‌منظور حصول بیشینه ظرفیت ناشی از به‌کارگیری رویکرد مقیاس‌بندی ولتاژ، ولتاژ منابع در سه سطح مختلف و با توجه به میزان متوسط فضای خالی حافظه میانگیرهای شبکه اعمال می‌شود. به این صورت که وقتی حافظه میانگیرها نزدیک به پر هستند، به‌کارگیری مقیاس‌بندی ولتاژ متوقف می‌شود. روش پیشنهادی به طور متوسط، میزان عدم دسترسی به داده در حافظه نهان را 16 درصد و مصرف انرژی را 5/12 درصد بهبود می‌دهد.
Voltage scaling is a widely used technique for energy saving, which increases the delay in the network in MPSoCs. To overcome this challenge, the volume of communication in the network should be reduced. In memory-intensive and communication-intensive applications, a considerable part of the network delay is due to the traffic originated from cache misses. In this paper, we employ the voltage scaling method in an adaptive way, while the free space of the NoC input buffers is used to reduce the traffic caused by the cache misses. Therefore, the proposed method increases the memory efficiency and reduces the energy consumption of the chip. To have an adaptive approach, the voltage is adjusted according to the average amount of free space of the NoC buffers, and the voltage scaling stops when the buffers are close to full. We achieve a 16% reduction in miss penalty on average, and a 12.5% improvement in power consumption.
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