Network-on-Chip with Adaptive Voltage Scaling for Power-Aware Memory Management in Multicore Processors
Subject Areas : electrical and computer engineeringSM Momeni 1 , HadiShahriar Shahhoseini 2 *
1 - Elec. Eng. School, Iran University of Science and Technology, Tehran, Iran
2 - Elec. Eng. School, Iran University of Science and Technology, Tehran, Iran
Keywords: Multiprocessor, system on chip, data management, cache memory, energy saving,
Abstract :
Voltage scaling is a widely used technique for energy saving, which increases the delay in the network in MPSoCs. To overcome this challenge, the volume of communication in the network should be reduced. In memory-intensive and communication-intensive applications, a considerable part of the network delay is due to the traffic originated from cache misses. In this paper, we employ the voltage scaling method in an adaptive way, while the free space of the NoC input buffers is used to reduce the traffic caused by the cache misses. Therefore, the proposed method increases the memory efficiency and reduces the energy consumption of the chip. To have an adaptive approach, the voltage is adjusted according to the average amount of free space of the NoC buffers, and the voltage scaling stops when the buffers are close to full. We achieve a 16% reduction in miss penalty on average, and a 12.5% improvement in power consumption.
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