Analysis and Evaluation of the Effect of Design Parameters on Timing Parameters and Power Consumption of Static Flip-Flop in 16 nm Technology Node
Subject Areas : electrical and computer engineering
E.
Mahmoodi
1
Morteza
Gholipour
2
(Babol Noshirvani University of Technology)
Keywords: Power consumptionstatic flip-floptiming parameters,
Abstract :
Flip-flop is one of the important elements in the digital circuit’s design, which its performance affects the speed and power of the system. In this paper, appropriate simulations are used to obtain the timing parameters of the static flip-flop and investigate the effect of the width of different transistors on these parameters. Then, the effects of the supply voltage and manufacturing process parameters variation on the performance of the flip-flop are investigated. The widths of transistors are determined based on the desired energy-delay product (EDP) and power-delay product (PDP) for these two cases separately. Then, the effect of voltage variations on the increase of EDP and PDP are investigated compared to the base flip-flop. We used a static D-type flip-flop in our simulations. The simulations were performed using the HSPICE in 16 nm technology node at 1 GHz frequency.
[1] S. Bernard, M. Belleville, J. Legat, A. Valentian, and D. Bol, "Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI," Microelectronics J., vol. 57, Issue C, pp. 76-86, Nov. 2016.
[2] H. Jiang, H. Zhang, T. R. Assis, B. Narasimham, B. L. Bhuva, W. T. Holman, and L. W. Massengill, "Single-event performance of sense-amplifier based flip-flop design in a 16-nm bulk FinFET CMOS process," IEEE Trans. on Nuclear Science, vol. 64, no. 1, pp. 477-482, Dec. 2017.
[3] L. Yang, X. Zhang, Q. Zhang, M. Tan, and Y. Yu, "A high-speed small-area pixel 16×16 ISFET array design using 0.35-μm CMOS process," Microelectronics J., vol. 79, pp. 107-112, Sept. 2018.
[4] Y. Li, L. Chen, I. Nofal, M. Chen, and R. Wong, "Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree," Microelectronics Reliability, vol. 87, pp. 24-32, Aug. 2018.
[5] M. Y. Tsai, P. Y. Kuo, J. F. Lin, and M. H. Sheu, "An ultra-low-power true single-phase clocking flip-flop with improved hold time variation using logic structure reduction scheme," in Proc. IEEE Int. Symp. on Circuits and Systems, ISCAS’18, 4 pp., Florence, Italy, 27-30 May 2018.
[6] B. Aparna and V. Anandi, "Design of a D flip flop for optimization of power dissipation using GDI technique," in Proc. 2nd IEEE Int. Conf. on Recent Trends in Electronics, Information & Communication Technology, RTEICT’17, pp. 172-177 Bangalore, India, 19-20 May 2017.
[7] H. NathSaha et al., "Performance optimization in flip flop circuit design," in Proc. IEEE 8th Annual Computing and Communication Workshop and Conf., CCWC’18, pp. 421-423, Las Vegas, NV, USA, 8-10 Jan. 2018.
[8] T. Lee, D. Z. Pan, and J. S. Yang, "Clock network optimization with multibit flip-flop generation considering multicorner multimode timing constraint," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 1, pp. 245-256, Apr. 2018.
[9] S. Heo and R. Krashinsky, "Activity-sensitive flip-flop and latch selection for reduced energy," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 9, pp. 1060-1064, Sept. 2007.
[10] Y. T. Liu, L. Y. Chiou, and S. J. Chang, "Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop," in Proc. IEEE Int. Symp. Circuits Systems, ISCAS’06, pp. 4329-4332, 21-24 May 2006.
[11] P. Zhao, T. K. Darwish, and M. A. Bayoumi, "High-performance and low-power conditional discharge flip-flop," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 477-484, May 2004.
[12] N. H. E. Weste and D. M. Harris, CMOS VLSI Design-a Circuits and Systems Perspective, 4th Edition, Addison-Wesley, 2015.
[13] A. R. Palaniappan and L. Siek, "Wide-input dynamic range 1 MHz clock ultra-low supply flip-flop," Electronics Letters, vol. 54, no. 15, pp. 938-939, 12 Jun. 2018.
[14] P. Bhattacharjee, B. Nath, and A. Majumder, "LECTOR based clock gating for low power multi-stage flip flop applications," in Proc. Int. Conf. on Electronics, Information, and Communication, ICEIC’17, pp. 106-109, Phuket, Thailand, 11-14 Jan. 2017.
[15] K. Liao, X. Cui, N. Liao, and T. Wang, "Design of D flip-flops with low power-delay product based on FinFET," in Proc. 12th IEEE Int. Conf. on Solid-State and Integrated Circuit Technology, ICSICT’14, 3 pp. 1-3, Guilin, China, 28-31 Oct. 2014.
[16] P. Dobriyal, K. Sharma, M. Sethi, and G. Sharma, "A high performance D-flip flop design with low power clocking system using MTCMOS technique," in Proc. 3rd IEEE Int. Advance Computing Conf., IACC’13, pp. 1524-1528, Ghaziabad, India, 22-23 Feb. 2013.
[17] M. A. Sobhan Bhuiyan, A. Mahmoudbeik, T. I. Badal, M. Bin Ibne Reaz, and L. F. Rahman, "Low power D flip-flop serial in/parallel out based shift register," in Proc. Int. Conf. on Advances in Electrical, Electronic and Systems Engineering, ICAEES’16, pp. 180-184, Putrajaya, Malaysia, 14-16 Nov. 2016.
[18] S. D. Pyle, H. Li, and R. F. DeMara, "Compact low-power instant store and restore D flip-flop using a self-complementing spintronic device," Electronics Letters, vol. 52, no. 14, pp. 1238-1240, 26 May 2016.
[19] -, Predictive Technology Model, [Online]. Available: http://ptm.asu.edu/