ارائه یک سیستم یک‌سوساز- اینورتری دوپایانه‌ای جدید به منظور کنترل مستقل دو بار سه‌فاز
محورهای موضوعی : مهندسی برق و کامپیوتر
مجتبي حيدري
1
(دانشگاه تربیت مدرس)
علی یزدیان ورجانی
2
(دانشگاه تربیت مدرس)
مصطفی محمدیان
3
(دانشگاه تربیت مدرس)
چکیده مقاله :
در این مقاله یک سیستم یک‌سوساز- اینورتری شامل یک یک‌سوساز دیودی سه‌فاز و یک اینورتر دوپایانه‌ای جدید برای کنترل مستقل دو بار سه‌فاز پیشنهاد می‌شود. این سیستم در مقایسه با سیستم‌های دیگر با کاربرد مشابه که پیش از این ارائه شده، دارای کمترین تعداد عناصر نیمه‌هادی بوده و برای کنترل دو بار سه‌فاز تنها از شش کليد نیمه‌هادی استفاده می‌کند. کاهش تعداد کليد‌ها در سیستم پیشنهادی و در نتیجه کاهش تعداد مدارهای درایو و همچنین سیستم خنک‌کنندگی آنها می‌تواند باعث کاهش قیمت تمام‌شده، کاهش وزن و حجم سیستم، کاهش تلفات نیمه‌هادی‌ها و در نتیجه افزایش بازده و قابلیت اطمینان به خصوص در کاربردهای با ولتاژ و توان متوسط و پایین شود. ابتدا ساختار جدید معرفی و پس از آن طرح PWM مبتنی بر موج حامل آن توسعه داده می‌شود. در ادامه، تحلیل تعیین مقدار ظرفیت بهینه خازن‌های لینک dc به منظور حداقل‌کردن ریپل ولتاژ لینک dc و همچنین کاهش THD و بهبود تعادل جریان شبکه انجام می‌گیرد. علاوه بر این تلفات سیستم پیشنهادی نیز مورد مطالعه قرار گرفته و نتایج با ساختارهای قبلی مقایسه می‌شود. در انتها برای تأیید صحت عملکرد ساختار پیشنهادی و همچنین تأیید تحلیل‌های صورت‌گرفته، نتایج شبیه‌سازی و آزمایشگاهی ارائه شده است.
In this paper a rectifier-inverter system including a three phase diode rectifier and a dual output inverter is proposed for independently supplying two three-phase loads. This system employs less number of semiconductor devices compared to former dual output inverters proposed in the literature and uses only six active switches for controlling two three-phase loads. Reducing the number of switches and hence drive and control circuits and also cooling system may result in a reduction in overall cost of the system, may reduce its semiconductor power loss and as a result increases efficiency and reliability especially in applications with low and medium voltage and power ratings. The new configuration is introduced and its carrier-based PWM schemes are developed. Analysis of sizing of the DC link capacitors is also performed so as to minimize the DC link voltage ripple, to reduce the value of DC link capacitors and to improve the grid current THD and the grid current balance. Furthermore, loss profile of the system is studied and the results are compared with counterpart topologies. Simulation and experimental results are presented to verify the authenticity of the theoretical model.
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