طراحی فلیپ‌فلاپ‌های جدید سه‌سطحی در نانوالکترونیک با استفاده از CNFET
محورهای موضوعی : مهندسی برق و کامپیوترکتایون رهبری 1 , سیدعلی حسینی 2 *
1 - انشکده مهندسی کامپیوتر و برق، دانشگاه آزاد اسلامی واحد یادگار امام خمینی
2 - دانشكده مهندسي كامپيوتر و برق، دانشگاه آزاد اسلامی واحد یادگار امام خمینی
کلید واژه: فلیپ‌فلاپ, مدارات سه‌سطحی, ترانزیستور نانوکربنی,
چکیده مقاله :
استفاده از مدارات چندسطحی می‌تواند باعث کاهش اتصالات داخل تراشه شود. کاهش اتصالات داخل تراشه‌ها باعث کاهش حجم تراشه و اتلاف توان در اتصالات می‌گردد. در سال‌های اخیر با توجه به توانایی نانوالکترونیک در طراحی مدارات چندسطحی، تحقیقاتی در این زمینه رونق گرفته است. مدارات ترتیبی، فلیپ‌فلاپ‌ها از اجزای مهم پردازنده‌ها و مدارات VLSI هستند. در این مقاله برای اولین بار، فلیپ‌فلاپ سه‌سطحی با پالس ژنراتور پیشنهاد گردیده و همین طور فلیپ‌فلاپ دیکد باینری به سه‌سطحی و نیز اولین فلیپ‌فلاپ با استفاده از بافر معرفی شده و سپس این فلیپ‌فلاپ‌ها با خودشان و مدارات قبلی مقایسه شده‌اند. همچنین از این فلیپ‌فلاپ‌ها در طراحی شمارنده سه‌سطحی استفاده شده است. نتایج شبیه‌سازی با نرم‌افزار HSPICE بیانگر عملکرد صحیح مدارات پیشنهادی می‌باشد. در مدل فلیپ‌فلاپ پالس ژنراتور STI %20، در فلیپ‌فلاپ SP %30 و در فلیپ‌فلاپ با بافر 30% بهبود در تأخیر و کاهش در تعداد ترانزیستور وجود دارد. همین طور در جدول مقایسه، مزایا و معایب هر کدام مورد بررسی قرار گرفته است.
Using multi-valued logic can reduce chip interconnections, which can have a direct effect on chip area and interconnections power consumption. In recent years, due to the ability of Nano electronics in the design of multi-level circuits, research in this field has flourished. The sequential circuits, flip-flops are important components of processors and VLSI circuits. In this paper, for the first time, a ternary flip-flop with a pulse generator has been proposed, and also a ternary binary-decode flip-flop and the first flip-flop using a buffer have been introduced. Then these flip-flops are compared with themselves and previous circuits. Also, these flip-flops have been used in the design of the ternary counter. The simulation results with HSPICE software show the correct performance of the proposed circuits. There is a 20% improvement in delay and a reduction in the number of transistors in the STI pulse generator flip-flop model, 30% in the SP flip-flop, and 30% in the buffer flip-flop. Also, in the comparison table, the advantages and disadvantages of each have been examined.
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