Analysis and Expansion of a Compact Model of Propagation Delay Time for Nano-CMOS NAND Gates in Response to Statistical Variability of Fabrication
Subject Areas : electrical and computer engineeringAbstract :
With shrinking transistor dimensions into nano meter scale, electrical parameters of transistors become more sensitive against statistical or random variations. Moreover, accurate estimation of these variations using “atomistic simulators” is time consuming and not a cost effective approach. In this paper for the first time, analytical models have been used to study the impacts of statistical variability of fabrication process on propagation delay time in a 35 nm CMOS NAND gate. With selecting appropriate set from analytical model’s parameters, the impact of statistical variability on the propagation delay time have been modeled and extended. Moreover, target analytical model has been benchmarked against statistical variability of fabrication process. The results obtained from extension of this model have been compared with the accurate atomistic simulations. It is observed that by applying different sets of parameters the maximum error of propagation delay time reaches to 8.7% against accurate atomistic simulations but by applying our proposed approach, Standard Deviation (SD) error of propagation delay is estimated to 2.4%. Also the SD error of propagation delay reaches to 9.9% when normal regenerated parameters have been used. Eventually using proposed algorithm which encompasses regenerated Gaussian parameters while taking the correlation factor into account, the SD error decreases to 1.6%.
References:
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[41] B. Cheng, et al., "Statistical-variability compact-modeling strategies for BSIM4 and PSP," IEEE Design & Test of Computers, vol. 27, no. 2, pp. 26-35, Mar. 2010.
[42] A. Asenov, B. Cheng, D. Dideban, U. Kovac, N. Moezi, C. Millar, et al., "Modeling and simulation of transistor and circuit variability and reliability," in Proc. IEEE Custom Integrated Circuits Conf., CICC'10, 8 pp., 19-22 Sept. 2010.
[43] U. Kovac, D. Dideban, B. Cheng, N. Moezi, G. Roy, and A. Asenov, "A novel approach to the statistical generation of non-normal distributed PSP compact model parameters using a nonlinear power method," in Proc. Int. Conf. on Simulation of Semiconductor Processes and Devices, pp. 125-128, 6-8 Sept. 2010.
[44] N. Moezi, D. Dideban, B. Cheng, S. Roy, and A. Asenov, "Impact of statistical parameter set selection on the statistical compact model accuracy: BSIM4 and PSP case study," Microelectronics J., vol. 44, no. 1, pp. 7-14, Jan. 2013.
[45] A. Krishnamoorthy and D. Menon, Matrix Inversion Using Cholesky Decomposition, arXiv preprint arXiv: 1111.4144, 2011.
[46] D. Dereniowski and M. Kubale, "Cholesky factorization of matrices in parallel and ranking of graphs," in Proc. Int. Conf. on Parallel Processing and Applied Mathematics, pp. 985-992, 2004.
[1] T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. of Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.
[2] S. Dutta, S. M. Shetti, and S. L. Lusky, "A comprehensive delay model for CMOS inverters," IEEE J. of Solid-State Circuits, vol. 30, no. 8, pp. 864-871, Aug. 1995.
[3] L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, "Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices," IEEE J. of Solid-State Circuits, vol. 33, no. 2, pp. 302-306, Feb. 1998.
[4] S. Gummalla, A. R. Subramaniam, Y. Cao, and C. Chakrabarti, "An analytical approach to efficient circuit variability analysis in scaled CMOS design," in Proc. 13th Int. Symp. on Quality Electronic Design, ISQED'12, pp. 641-647, 19-21 Mar. 2012.
[5] P. Liu, Y. B. Kim, and Y. J. Lee, "An accurate timing model for nano CMOS circuit considering statistical process variation," in Proc. ISOCC Conf., pp. 269-272, 2007.
[6] Y. Ye, S. Gummalla, C. C. Wang, C. Chakrabarti, and Y. Cao, "Random variability modeling and its impact on scaled CMOS circuits," J. of Computational Electronics, vol. 9, no. 3-4, pp. 108-113, Dec. 2010.
[7] M. Alioto, G. Palumbo, and M. Pennisi, "Understanding the effect of process variations on the delay of static and domino logic," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 5, pp. 697-710, May 2010.
[8] P. Liu, Y. B. Kim, and Y. J. Lee, "An accurate analytical propagation delay model of nano CMOS circuits," in Proc. ISOCC Conf., pp. 200-203, 2007.
[9] W. F. Lu and L. I. Sun, "Compact modeling of response time and random-dopant-fluctuation-induced variability in nanoscale CMOS inverter," Microelectronics J., vol. 45, no. 6, pp. 678-682, Jun. 2014.
[10] A. Nabavi-Lishi and N. C. Rumin, "Inverter models of CMOS gates for supply current and delay evaluation," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 10, pp. 1271-1279, Oct. 1994.
[11] M. Na, E. Nowak, W. Haensch, and J. Cai, "The effective drive current in CMOS inverters," in Proc. Int. Electron Devices Meeting, IEDM'02, pp. 121-124, 8-11 Dec. 2002.
[12] J. Chang and L. G. Johnson, "A novel delay model of CMOS VLSI circuits," in Proc. 49th IEEE Int. Midwest Symp. on Circuits and Systems, pp. 481-485, 6-9 Aug. 2006.
[13] J. L. Rossello and J. Segura, "An analytical charge-based compact delay model for submicrometer CMOS inverters," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 51, no. 7, pp. 1301-1311, Jul. 2004.
[14] K. O. Jeppson, "Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay," IEEE J. of Solid-State Circuits, vol. 29, no. 6, pp. 646-654, Jun. 1994.
[15] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 2, pp. 250-260, Jan. 2010.
[16] A. A. Hamoui and N. C. Rumin, "An analytical model for current, delay, and power analysis of submicron CMOS logic circuits," IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 10, pp. 999-1007, Oct. 2000.
[17] N. Hedenstierna and K. O. Jeppson, "CMOS circuit speed and buffer optimization," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, no. 2, pp. 270-281, Mar. 1987.
[18] L. Bisdounis, S. Nikolaidis, and O. Loufopavlou, "Propagation delay and short-circuit power dissipation modeling of the CMOS inverter," IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 45, no. 3, pp. 259-270, Mar. 1998.
[19] A. Hirata, H. Onodera, and K. Tamaru, "Estimation of short-circuit power dissipation for static CMOS gates," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. 79, no. 3, pp. 304-311, Mar. 1996.
[20] A. Chatzigeorgiou and S. Nikolaidis, "Collapsing the transistor chain to an effective single equivalent transistor," in Proc. Design, Automation and Test in Europe, pp. 2-6, 23-26 Feb. 1998.
[21] S. Kang and H. Chen, "A global delay model for domino CMOS circuits with application to transistor sizing," International J. of Circuit Theory and Applications, vol. 18, no. 3, pp. 289-306, May 1990.
[22] B. S. Cherkauer and E. G. Friedman, "Channel width tapering of serially connected MOSFET's with emphasis on power dissipation," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 1, pp. 100-114, Mar. 1994.
[23] J. Roldan, F. Gamiz, J. Lopez-Villanueva, P. Cartujo, and J. Carceller, "A model for the drain current of deep submicrometer MOSFETs including electron-velocity overshoot," IEEE Trans. on Electron Devices, vol. 45, no. 10, pp. 2249-2251, Oct. 1998.
[24] A. Benfdila and F. Balestra, "On the drain current saturation in short channel MOSFETs," Microelectronics J., vol. 37, no. 7, pp. 635-641, Jul. 2006.
[25] Y. Cao and L. T. Clark, "Mapping statistical process variations toward circuit performance variability: an analytical modeling approach," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 1866-1873, Oct. 2007.
[26] V. Wang, K. Agarwal, S. R. Nassif, K. J. Nowka, and D. Markovic, "A simplified design model for random process variability," IEEE Trans. on Semiconductor Manufacturing, vol. 22, no. 1, pp. 12-21, Feb. 2009.
[27] M. H. Han, Y. Li, and C. H. Hwang, "The impact of high-frequency characteristics induced by intrinsic parameter fluctuations in nano-MOSFET device and circuit," Microelectronics Reliability, vol. 50, no. 5, pp. 657-661, May 2010.
[28] E. Maricau and G. Gielen, "Computer-aided analog circuit design for reliability in nanometer CMOS," IEEE J. on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 1, pp. 50-58, Mar. 2011.
[29] X. Yuan, T. Shimizu, U. Mahalingam, J. S. Brown, K. Z. Habib, D. G. Tekleab, et al., "Transistor mismatch properties in deep-submicrometer CMOS technologies," IEEE Trans. on Electron Devices, vol. 58, no. 2, pp. 335-342, Feb. 2011.
[30] X. Wang, F. Adamu-Lema, B. Cheng, and A. Asenov, "Geometry, temperature, and body bias dependence of statistical variability in 20-nm bulk CMOS technology: a comprehensive simulation analysis," IEEE Trans. on Electron Devices, vol. 60, no. 5, pp. 1547-1554, Apr. 2013.
[31] M. Saremi, B. Ebrahimi, A. A. Kusha, and M. Saremi, "Process variation study of ground plane SOI MOSFET," in Proc. 2nd Asia Symp. on Quality Electronic Design, ASQED'10, pp. 66-69, 3-4 Aug. 2010.
[32] M. Saremi, B. Ebrahimi, and A. Afzali-Kusha, "Ground plane SOI MOSFET based SRAM with consideration of process variation," in Proc. IEEE Int. Conf. on Electron Devices and Solid-State Circuits, EDSSC'10, 4 pp., 15-17 Dec. 2010.
[33] A. Asenov, et al., "Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits," in Proc. IEEE Int. Symp. on Circuits and Systems, ISCAS'15, pp. 2449-2452, 24-27 May 2015.
[34] L. Gerrer, et al., "Interplay between statistical reliability and variability: a comprehensive transistor-to-circuit simulation technology," in Proc. IEEE Int. Reliability Physics Symp., IRPS'13, 5 pp., 14-18 Apr. 2013.
[35] L. Gerrer, et al., "Accurate simulation of transistor-level variability for the purposes of TCAD-based device-technology cooptimization," IEEE Trans. on Electron Devices, vol. 62, no. 6, pp. 1739-1745, Apr. 2015.
[36] S. M. Amoroso, L. Gerrer, R. Hussin, F. Adamu-Lema, and A. Asenov, "Time-dependent 3-D statistical KMC simulation of reliability in nanoscale MOSFETs," IEEE Trans. on Electron Devices, vol. 61, no. 6, pp. 1956-1962, Apr. 2014.
[37] X. Wang, A. R. Brown, B. Cheng, and A. Asenov, "Statistical variability and reliability in nanoscale FinFETs," in Proc. IEEE Int. Electron Devices Meeting, IEDM'11, 4 pp., 5-7 Dec. 2011.
[38] E. Bazizi, , et al., "Advanced TCAD simulation of local mismatch in 14 nm CMOS technology FinFETs," in Proc. Int. Conf. on Simulation of Semiconductor Processes and Devices, SISPAD'15, pp. 341-344, 9-11 Sept. 2015.
[39] Y. Wang and M. Zwolinski, "Analytical transient response and propagation delay model for nanoscale CMOS inverter," in Proc. IEEE Int. Symp. on Circuits and Systems, pp. 2998-3001, 24-27 May 2009.
[40] A. R. Brown, et al., "Use of density gradient quantum corrections in the simulation of statistical variability in MOSFETs," J. of Computational Electronics, vol. 9, no. 3-4, pp. 187-196, Sept. 2010.
[41] B. Cheng, et al., "Statistical-variability compact-modeling strategies for BSIM4 and PSP," IEEE Design & Test of Computers, vol. 27, no. 2, pp. 26-35, Mar. 2010.
[42] A. Asenov, B. Cheng, D. Dideban, U. Kovac, N. Moezi, C. Millar, et al., "Modeling and simulation of transistor and circuit variability and reliability," in Proc. IEEE Custom Integrated Circuits Conf., CICC'10, 8 pp., 19-22 Sept. 2010.
[43] U. Kovac, D. Dideban, B. Cheng, N. Moezi, G. Roy, and A. Asenov, "A novel approach to the statistical generation of non-normal distributed PSP compact model parameters using a nonlinear power method," in Proc. Int. Conf. on Simulation of Semiconductor Processes and Devices, pp. 125-128, 6-8 Sept. 2010.
[44] N. Moezi, D. Dideban, B. Cheng, S. Roy, and A. Asenov, "Impact of statistical parameter set selection on the statistical compact model accuracy: BSIM4 and PSP case study," Microelectronics J., vol. 44, no. 1, pp. 7-14, Jan. 2013.
[45] A. Krishnamoorthy and D. Menon, Matrix Inversion Using Cholesky Decomposition, arXiv preprint arXiv: 1111.4144, 2011.
[46] D. Dereniowski and M. Kubale, "Cholesky factorization of matrices in parallel and ranking of graphs," in Proc. Int. Conf. on Parallel Processing and Applied Mathematics, pp. 985-992, 2004.