A Novel Source/Drain side Double Recessed Gate 4H-SiC MESFET with n-Buried Layer in the Channel
Subject Areas : electrical and computer engineeringS. M. Razavi 1 * , Seyed-Hamid Zahiri 2
1 -
2 - University of Birjand
Abstract :
A new structure named as source/drain sides-double recessed gate with N-buried layer in the channel (SDS-DRG) silicon carbide (SiC) based metal semiconductor field effect transistor (MESFET) is presented in this study. Important parameters such as short channel effect, maximum DC trans-conductance, drain current and breakdown voltage of the proposed structure are simulated and compared with those of the source side-double recessed gate (SS-DRG) and drain side-double recessed gate (DS-DRG) 4H-SiC MESFETs. Our simulation results reveal that reducing the channel thickness under the gate at the SDS-DRG structure improves the maximum DC trans-conductance and reduces the short channel effects compared to SS-DRG and DS-DRG structures. Reducing the channel thickness under the gate at the drain side of the SDS-DRG structure is used to enhance the breakdown voltage in comparison with the SS-DRG structure. Also, N-buried layer with larger doping concentration in the SDS-DRG structure improves the saturated drain current compared to SS-DRG and DS-DRG structures.
[1] J. Spann, V. Kushner, T. J. Thornton, J. Yang, A. Balijepalli, H. J. Barnaby, X. J. Chen, D. Alexander, W. T. Kemp, S. J. Sampson, and M. E. Wood, "Total dose radiation response of CMOS compatible SOI MESFETs," IEEE Trans. Nuclear Science, vol. 52, no. 6, pp. 2398-2402, Dec. 2005.
[2] C. S. Hou and C. Y. Wu, "A 2-D analytic model for the threshold-voltage of fully depleted short gate-length Si-SOI MESFET," IEEE Trans. Electron Devices, vol. 42, no. 12, pp. 2156-2162, Dec. 1995.
[3] H. Hjelmgren, F. Allerstam, K. Andersson, P. A. Nilsson, and N. Rorsman, "Transient simulation of microwave SiC MESFETs with improved trap models," IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 729-732, Mar. 2010.
[4] S. Sriram, et al., "High-gain SiC MESFETs using source-connected field plates," IEEE Trans. Electron Devices, vol. 30, no. 9, pp. 952-953, Sept. 2009.
[5] C. L. Zhu, Rusli and P. Zhao, "Dual-channel 4H-SiC metal semiconductor field effect transistors," Solid-State Electronic, vol. 51, no. 3, pp. 343-346, Mar. 2007.
[6] Rusli, C. L. Zhu, P. Zhao, and J. H. Xia, "Characterization of SiC MESFETs with narrow channel layer," Microelectronic Engineering, vol. 83, no. 1, pp. 72-74, Jan. 2006.
[7] J. Zhang, Y. Ye, C. Zhou, X. Luo, B. Zhang, and Z. Li, "High breakdown voltage 4H-SiC MESFETs with floating metal strips," Microelectronic Engineering, vol. 85, no. 1, pp. 89-92, Jan. 2008.
[8] X. Deng, B. Zhang, Z. Li, and Z. Chen, "Two-dimensional analysis of the surface state effects in 4H-SiC MESFETs," Microelectronic Engineering, vol. 85, no. 2, pp. 295-299, Feb. 2008.
[9] A. A. Orouji, S. M. Razavi, S. E. Hosseini, and H. A. Moghadam, "Investigation of the novel attributes in double recessed gate SiC MESFETs at drain side," Semicond. Sci. Technol., vol. 26, no. 11, pp. 115001-115005, Oct. 2011.
[10] L. Yang, Y. Zhang, and C. Yu, "A compact model describing the effect of p-buffer layer on the I-V characteristics of 4H-SiC power MESFETs," Solid-State Electronics, vol. 49, no. 4, pp. 517-523, Feb. 2005.
[11] K. Andersson, M. Sudow, P. A. Nilsson, E. Sveinbjornsson, H. Hjelmgren, J. Nilsson, J. Stahl, H. Zirath, and N. Rorsman, "Fabrication and characterization of field-plated buried-gate SiC MESFETs," IEEE Electron Device Lett., vol. 27, no. 7, pp. 573-575, Jul. 2006.
[12] , ATLAS User's Manual, Device Simulation Software, Silvaco International, Sep. 2005.
[13] M. Ruff, H. Mitlehner, and R. Helbig, "SiC devices: physics and numerical simulation," IEEE Trans. Electron Devices, vol. 41, no. 6, pp. 1040-1054, Jun. 1994.
[14] H. Linewih, S. Dimitrijev, and K. Y. Cheong, "Channel-carrier mobility parameters for 4H SiC MOSFETs," Microelectronics Rel., vol. 43, no. 3, pp. 405-411, Mar. 2003.
[15] B. J. Baliga, Modern Power Devices, New York: Wiley Interscience, 1987.
[16] S. E. J. Mahabadi, A. A. Orouji, P. Keshavarzi, and H. A. Moghadam, "A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage," Semicond. Sci. Technol., vol. 26, no. 9, pp. 95005-950016, Jul. 2011.
[17] C. S. Chang, D. Y. S. Day, and S. Chan, "An analytical two-dimentional simulation for the GaAs MESFET drain-induced barrier lowering: a short channel effect," IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 1182-1186, May 1990.
[18] P. Pandey, B. B. Pal, and S. Jit, "A new 2-D model for the potential distribution and threshold voltage of fully depleted short-channel Si-SOI MESFETs," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 246-254, Feb. 2004.
[19] C. L. Zhu, Rusli, C. C. Tin, G. H. Zhang, S. F. Yoon, and J. Ahn, "Improved performance of SiC MESFETs using double-recessed structure," Microelectronic Engineering, vol. 83, no. 1, pp. 92-95, Jan. 2006.
[20] J. Zhang, X. Luo, Z. Li, and B. Zhang, "Improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region," Microelectronic Engineering, vol. 84, no. 12, pp. 2888-2891, Dec. 2007.
[21] M. K. Verma and B. B. Pal, "Analysis of buried gate MESFET under dark and illumination," IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2138-2142, Sep. 2001.