Sub-Threshold 8T SRAM Cell with Improved Write-Ability and Read Stability
Subject Areas : electrical and computer engineering
Gh.
Pasandi
1
(University of Tehran)
S. M.
Fakhraie
2
(University of Tehran)
Keywords: Layout low-power memory sense-amplifier SRAM,
Abstract :
Conventional 6T SRAM cell suffers from poor write-ability and poor read stability at low supply voltages. In this paper a new 8T SRAM cell is proposed that achieves improved write-ability and increased read stability at the same time. The proposed SRAM cell can successfully operate at small supply voltages as low as 275 mV whereas conventional 6T SRAM cell cannot. To show the prominence of the proposed cell and for better comparison, our SRAM cell, conventional 6T SRAM cell, and also three other SRAM cells from recent literature are designed in a 90nm industrial CMOS technology with the same conditions. Simulation results show that the proposed 8T SRAM cell decreases write and read delays by 47.5% and 50%, respectively at supply voltage of 800 mV. Our SRAM cell also improves power consumption for single write operation by 40% over the best design at supply voltage of 800 mV. Among the five designs compared, our design is the only one that operates at supply voltages as low as 275 mV. Finally, layout of the proposed SRAM cell is developed in 180 nm industrial CMOS technology and results of post-layout simulations are discussed.
[1] A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-Threshold Design for Ultra Low Power Systems, Springer, 2005.
[2] K. Wang, Ultra Low Power Fault Tolerant SRAM Design in 90 nm CMOS, M.Sc. Thesis, Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, Saskatchewan, Canada, 2010.
[3] L. Turicchia, et al., "Ultra low power electronics for noninvasive medical monitoring," in Proc. IEEE Custom Integrated Circuits Conf., CICC'09, pp. 85-92, 13-16 Sep. 2009.
[4] J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: a Design Perspective, Prentice-Hall, Inc., 2003.
[5] T. H. Kim, Design Techniques for Ultra-Low Voltage Sub-Threshold Circuits and on-Chip Reliability Monitoring, Ph.D Thesis, Graduate School, University of Minnesota, Oct. 2010.
[6] B. H. Calhoun and A. Chandrakasan, "A 256 kb sub-threshold SRAM using 65 nm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf., ISSCC'06. pp. 628-629, 6-9 Feb. 2006.
[7] L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight et al., "Stable SRAM cell design for the 32 nm node and beyond," in Proc. IEEE Symp. on VLSI Technology, pp. 128-129, 14-16 Jun. 2005.
[8] J. Chen, L. T. Clark, and T. Chen, "An ultra-low-power memory with a sub-threshold power supply voltage," IEEE J. of Solid-State Circuits, vol. 41, no. 10, pp. 2344-2353, Oct. 2006.
[9] S. Tavva, A Novel Variation-Tolerant 9 T SRAM Design for Nanoscale CMOS, M.Sc. Thesis, Department of Computer Engineering, Kate Gleason College of Engineering, Rochester Institute of Technology, Rochester, New York, May 2010.
[10] T. Kim, J. Liu, J. Keane, and C. Kim, "A 0.2 V, 480 kb sub-threshold SRAM with 1 k cells per bit-line for ultra-low-voltage computing," IEEE J. of Solid-State Circuits, vol. 43, no. 2, pp. 518-529, Feb. 2008.
[11] G. Pasandi and S. M. Fakhraie, "A new sub-threshold 7 T SRAM cell design with capability of bit-interleaving in 90 nm CMOS," in Proc. 21st Iranian Conf. on Electrical Engineering, 6 pp., Mashhad, Iran, 14-16 May 2013.
[12] A. Neale, Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation, M.Sc. Thesis, Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada, 2010.
[13] M. Sharifkhani and M. Sachdev, "Segmented virtual ground architecture for low-power embedded SRAM," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 2, pp. 196-205, Feb. 2007.s [14] J. P. Kulkarni, K. Kim, and K. Roy, "A 160 mV robust schmitt trigger based sub-threshold SRAM," IEEE J. of Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007.
[15] A. Islam and M. Hasan, "Leakage characterization of 10 T SRAM cell," IEEE Trans. on Electron Devices, vol. 59, no. 3, pp. 631-638, Mar. 2012.
[16] Z. Liu and V. Kursun, "Characterization of a novel nine-transistor SRAM cell," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 4, pp. 488-492, Apr. 2008.
[17] J. M. Rabaey, Low Power Essentials, Springer, 2009.
[18] F. M. Long et al., "Comparison of 4 T and 6 T FinFET SRAM cells for subthreshold operation considering variability - a model-based approach," IEEE Trans. on Electron Devices, vol. 58, no. 3, pp. 609-616, Mar. 2011.
[19] Predictive Technology Model (PTM), Available: http://ptm.asu.edu/