جمع‌کننده نافرار و توان پایین مبتنی بر فناوری اسپینترونیک برای پیاده‌سازی محاسبات در حافظه
محورهای موضوعی : مهندسی برق و کامپیوترعبداله امیرانی 1 , کیان جعفری 2 * , رامین رجایی 3
1 - دانشگاه شهید بهشتی
2 - دانشگاه شهید بهشتی
3 - دانشگاه شهید بهشتی
کلید واژه: پیوند تونل مغناطیسیطراحی توان پایینفناوری اسپینترونیکمحاسبات در حافظهمدارهای ترکیبی MTJ/CMOS,
چکیده مقاله :
با پیشرفت فناوری و کوچک‌شدن اندازه ترانزیستورها به خصوص در فناوری‌های زیر 90 نانومتر مصرف توان ایستای بالا به علت افزایش نمایی جریان نشتی ترانزیستورها به یکی از بزرگ‌ترین مشکلات مدارهای مبتنی بر فناوری CMOS تبدیل شده است. افزاره‌های اسپینترونیک مانند پیوند تونل مغناطیسی (MTJ) با توجه به ویژگی‌های منحصربه‌فردشان از جمله مصرف توان ایستای پایین، نافراربودن، طول عمر زیاد، سازگاری با ترانزیستور‌های CMOS و امکان ساخت در چگالی‌های بالا یکی از گزینه‌های مورد توجه برای طراحی مدارهای ترکیبی MTJ/CMOS و غلبه بر معضل مصرف توان ایستای بالا در مدارهای مبتنی بر فناوری CMOS است. در این مقاله یک تمام جمع‌کننده ترکیبی MTJ/CMOS کاملاً نافرار و توان پایین برای پیاده‌سازی محاسبات در حافظه ارائه شده است. نتایج شبیه‌سازی‌ها نشان می‌دهد که تمام جمع‌کننده نافرار پیشنهادی نسبت به تمام جمع‌کننده‌های نافرار موجود حداقل 50 درصد سریع‌تر بوده، حاصل‌ضرب توان در تاخیر آن 39 درصد کمتر است و سربار سخت‌افزاری زیادی نیز به مدار تحمیل نمی‌کند.
As technology nodes shrink below 90 nm, high static power consumption has become one of the biggest problems of CMOS based circuits due to the exponential leakage current of transistors. Spintronic devices such as magnetic tunnel junction (MTJ) due to their fascinating features such as low static power consumption, non-volatility, high endurance, compatibility with CMOS transistors and high-density fabrication are one of the promising candidate for designing hybrid MTJ/CMOS circuits and overcoming high static power consumption of CMOS based circuits. In this paper, a fully nonvolatile and low power hybrid MTJ/CMOS full-adder circuit for Realization of Process in Memory is proposed. The simulation results show that all the proposed circuit is at least 50% faster than all previous counterparts, the power output delay is 39% lower than the previous design, and does not impose high hardware overhead.
[1] N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. Irwin, M. Kandemir, and V. Narayanan, "Leakage current: Moore's law meets static power," Computer, vol. 36, no. 12, pp. 68-75, Dec. 2003.
[2] B. Hoefflinger, "ITRS: the international technology roadmap for semiconductors," The Frontiers Collection, pp. 161-174, 2011.
[3] R. Rajaei and A. Amirany, "Reliable, high-performance, and nonvolatile hybrid SRAM/MRAM-based structures for reconfigurable nanoscale logic devices," J. of Nanoelectronics and Optoelectronics, vol. 13, no. 9, pp. 1271-1283, Mar. 2018.
[4] W. Zhao, E. Belhaire, C. Chappert, and P. Mazoyer, "Power and area optimization for run-time reconfiguration system on programmable.
[5] chip based on magnetic random access memory," IEEE Trans. on Magnetics, vol. 45, no. 2, pp. 776-780, Feb. 2009.
[6] C. Chappert, A. Fert, and F. Van Dau, "The emergence of spin electronics in data storage," Nature Materials, vol. 6, no. 11, pp. 813-823, Nov. 2007.
[7] S. Ikeda, et al., "Tunnel magnetoresistance of 604% at 300 K by suppression of Ta diffusion in CoFeB∕MgO∕CoFeB pseudo-spin-valves annealed at high temperature," Applied Physics Letters, vol. 93, no. 8, p. 082508, Aug, 2008.
[8] .J. Slonczewski, "Conductance and exchange coupling of two ferromagnets separated by a tunneling barrier," Physical Review B, vol. 39, no. 10, pp. 6995-7002, Apr. 1989.
[9] A. Mochizuki, "TMR-based logic-in-memory circuit for low- power VLSI," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. 88, no. 6, pp. 1408-1415, Aug. 2005.
[10] R. Rajaei, "Radiation-hardened design of nonvolatile MRAM-based FPGA," IEEE Trans. on Magnetics, vol. 52, no. 10, pp. 1-10, Oct. 2016.
[11] W. Zhao, E. Belhaire, C. Chappert, and P. Mazoyer, "Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit," ACM Trans. on Embedded Computing Systems, vol. 9, no. 2, pp. 1-16, Oct. 2009.
[12] A. Amirany, F. Marvi, K. Jafari, and R. Rajaei, "Nonvolatile spin-based radiation hardened retention latch and flip-flop," IEEE Trans. on Nanotechnology, vol. 18, no. 5, pp. 1089-1096, Oct. 2019.
[13] R. Rajaei, "Design of a radiation hardened register file for highly reliable microprocessors," International J. of Engineering and Manufacturing, vol. 6, no. 5, pp. 11-21, Feb. 2016.
[14] W. Kang, Y. Ran, W. Lv, Y. Zhang, and W. Zhao, "High-speed, low-power, magnetic non-volatile flip-flop with voltage-controlled, magnetic anisotropy assistance," IEEE Magnetics Letters, vol. 7, pp. 1-5, Aug. 2016.
[15] D. Suzuki and T. Hanyu, "Magnetic-tunnel-junction based low-energy nonvolatile flip-flop using an area-efficient self-terminated write driver," J. of Applied Physics, vol. 117, no. 17, pp. 17B504, Oct. 2015.
[16] A. Amirany and R. Rajaei, "Nonvolatile, spin-based, and low-power inexact full adder circuits for computing-in-memory image processing," Spin, vol. 9, no. 3, p. 1950013, Aug. 2019.
[17] E. Deng, Y. Wang, Z. Wang, J. Klein, B. Dieny, G. Prenat, and W. Zhao, "Robust magnetic full-adder with voltage sensing 2T/2MTJ cell," in Proc IEEE/ACM Int. Symp. on Nanoscale Architectures, NANOARCH´15), Boston, MA, USA, 8-10 Jul. 2015.
[18] R. Rajaei and S. Bakhtavari Mamaghani, "Ultra-low power, highly reliable, and nonvolatile hybrid MTJ/CMOS based full-adder for future VLSI design," IEEE Trans. on Device and Materials Reliability, vol. 17, no. 1, pp. 213-220, Dec. 2017.
[19] E. Deng, et al., "Low power magnetic full-adder based on spin transfer torque MRAM," IEEE Trans. on Magnetics, vol. 49, no. 9, pp. 4982-4987, Sept. 2013.
[20] H. –P. Trinh, et al., "Magnetic adder based on racetrack memory," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 60, no. 6, pp. 1469-1477, Jun. 2013.
[21] A. Amirany and R. Rajaei, "Fully nonvolatile and low power full adder based on spin transfer torque magnetic tunnel junction with spin-hall effect assistance," IEEE Trans. on Magnetics, vol. 54, no. 12, pp. 1-7, Oct. 2018.
[22] A. Amirany and R. Rajaei, "Spin-based fully nonvolatile full-adder circuit for computing in memory," Spin, vol. 9, no. 1, p. 1950007, Apr. 2019.
[23] O. Hassan, R. Faria, K. Y. Camsari, J. Z. Sun, and S. Datta, "Low-barrier magnet design for efficient hardware binary stochastic neurons," IEEE Magnetics Letters, vol. 10, pp. 1-5, Apr. 2019.
[24] C. Pan and A. Naeemi, "A proposal for energy-efficient cellular neural network based on spintronic devices," IEEE Trans. on Nanotechnology, vol. 15, no. 5, pp. 820-827, Sept. 2016.
[25] A. Amirany, M. H. Moaiyeri, and K. Jafari, "Process-in-memory using a magnetic-tunnel-junction synapse and a neuron based on a carbon nanotube field-effect transistor," IEEE Magnetics Letters, vol. 10, pp. 1-5, Dec. 2019.
[26] M. A. Abeed and S. Bandyopadhyay, "Low energy barrier nanomagnet design for binary stochastic neurons: design challenges for real nanomagnets with fabrication defects," IEEE Magnetics Letters, vol. 10, pp. 1-5, Jan. 2019.
[27] "Predictive Technology Model," Predictive Technology Model, 2017. [Online]. Available: http://ptm.asu.edu/modelcard/HP/32nm_HP.pm. [Accessed: 25- Oct- 2017].
[28] Z. Wang, W. Zhao, E. Deng, J. Klein, and C. Chappert, "Perpendicular-anisotropy magnetic tunnel junction switched by spin-hall-assisted spin-transfer torque," J. of Physics D: Applied Physics, vol. 48, no. 6, p. 065001, Feb. 2015.
[29] A. Amirany and R. Rajaei, "Low power, and highly reliable single event upset immune latch for nanoscale CMOS technologies," in Proc. Iranian Conf. on Electrical Engineering, ICEE’18, pp. 103-107, Mashhad, Iran, 8-10 May 2018.