کاهش جریان خاموشی در ترانزیستور اثر میدان بدون پیوند دوگیتی نانومتری با استفاده از مهندسی آلایش میانه کانال
محورهای موضوعی : مهندسی برق و کامپیوتر
سروناز کلانتری
1
(دانشگاه آزاد اسلامی واحد ابهر)
مهدی وادی‌زاده
2
(دانشگاه آزاد اسلامی واحد ابهر)
چکیده مقاله :
مقیاس‌بندی طول کانال، جریان نشتی افزاره بدون پیوند دوگیتی (DGJL-FET) را افزایش می‌دهد و در نتیجه توان مصرفی افزاره در حالت خاموش افزایش می‌یابد. در این مقاله، ساختار نوینی برای کاهش جریان نشتی افزاره DGJL-FET پیشنهاد شده که Modified DGJL-FET نامیده می‌شود. در ساختار Modified DGJL-FET آلایش کانال در زیر گیت با آلایش سورس و درین یکسان، اما بیشتر از میانه کانال است. نتایج شبیه‌سازی نشان می‌دهد با کاهش ضخامت لایه آلاییده زیر گیت، D، جریان نشتی کاهش می‌یابد. برای افزاره پیشنهادشده با طول کانال nm 10 جریان خاموشی دو دهه بزرگی کمتر از افزاره Regular DGJL-FET است. عملکرد افزاره Regular DGJL-FET و Modified DGJL-FET برای طول کانال‌های مختلف بر حسب نسبت جریان حالت روشنی به جریان حالت خاموشی (ION/IOFF)، شیب زیر آستانه (SS) و تأخیر ذاتی گیت مقایسه شده است. برای افزاره Modified DGJL-FET، D و آلایش میانه کانال به عنوان پارامترهای اضافی برای بهبود عملکرد افزاره در رژیم نانومتر در نظر گرفته شده است. نتایج شبیه‌سازی نشان می‌دهد در افزاره پیشنهادشده با طول کانال nm 15، SS و ION/IOFF نسبت به افزارهRegular DGJL-FET به ترتیب 14% و 6e10 دهه بزرگی بهبود یافته است.
Scaling the channel length leads to the increased leakage current of double gate junctionless field effect transistor (DGJL-FET) and, as a result, the increased power consumption in OFF-state. The present paper proposes a new structure for reducing the leakage current in DGJL-FET, which is called modified DGJL-FET. In this structure, the channel doping under the gate is the same as the drain and source doping but higher than the mid-channel doping. The simulation results indicated that reducing the thickness of the doped layer under the gate, D, resulted in the reduced OFF-state current. For the proposed device with 10 nm channel length, the OFF-state current is less than that in the regular DGJL-FET by two orders of magnitude. Performance of the regular DGJL-FET and modified DGL-FET for different channel lengths is compared based on the IOFF/ION ratio, sub-threshold slope (SS), and intrinsic gate delay. For modified DGJL-FET, the mid-channel doping and Dare considered as additional parameters for improving the device’s performance in nanometer regime. The simulation results indicated that in the proposed device with channel length of 15 nm, values of SS and IOFF/ION ratio are improved compared to the regular DGJL-FET by 14% and 106 orders of magnitude, respectively.
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