Reducing OFF-State Current in Nano-Scale Double Gate Junctionless Field Effect Transistor (DGJL-FET) Using Doping Engineering of Channel Region
Subject Areas : electrical and computer engineeringAbstract :
Scaling the channel length leads to the increased leakage current of double gate junctionless field effect transistor (DGJL-FET) and, as a result, the increased power consumption in OFF-state. The present paper proposes a new structure for reducing the leakage current in DGJL-FET, which is called modified DGJL-FET. In this structure, the channel doping under the gate is the same as the drain and source doping but higher than the mid-channel doping. The simulation results indicated that reducing the thickness of the doped layer under the gate, D, resulted in the reduced OFF-state current. For the proposed device with 10 nm channel length, the OFF-state current is less than that in the regular DGJL-FET by two orders of magnitude. Performance of the regular DGJL-FET and modified DGL-FET for different channel lengths is compared based on the IOFF/ION ratio, sub-threshold slope (SS), and intrinsic gate delay. For modified DGJL-FET, the mid-channel doping and Dare considered as additional parameters for improving the device’s performance in nanometer regime. The simulation results indicated that in the proposed device with channel length of 15 nm, values of SS and IOFF/ION ratio are improved compared to the regular DGJL-FET by 14% and 106 orders of magnitude, respectively.
[1] K. Natori, "Ballistic metal-oxide-semiconductor field effect transistors," J. Appl. Phys, vol. 76, no. 8, pp. 4879-4890, Nov. 1994.
[2] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistor," in Proc. of Symp. VLSI Technology, Digest of Technical, pp. 174-175, 13-15 Jun. 2000.
[3] A. Wagadre and S. Mane, "Design & performance analysis of DG-MOSFET for reduction of short channel effect over bulk MOSFET at 20 nm," International Journal of EngineeringResearch and Applications, vol. 4, pp. 30-34, Jul. 2014.
[4] D. Sapna and B. Mehandia, "Study of electrical characteristics of SOI MOSFET using silvaco tcad simulator," Technology and Sciences, vol. 1, no. 1, pp. 15-18, Jul. 2012.
[5] M. M. Khatamia, M. Shalchiana, and M. Kolahdouz, "Reducing parasitic capacitance of strained Si nano p-MOSFET by control of virtual substrate doping," in Proc. 5th Int. Congress on Nanoscience & Nanotechnology, ICCN'14, pp. 247-250, Aug. 2014.
[6] M. Rahman, P. Narayanan, and C. A. Moritz, Metal-Gated Junctionless Nanowire Transistors. arXiv preprint arXiv:1404.0296, Apr. 2014.
[7] W. Maly, et al., "Twin Gate, Vertical Slit FET (VeSFET) for highly periodic layout and 3D integration," in Proc. of 18th Int. Conf. on Mixed Design of Integrated Circuits and Systems, MIXDES'11, pp. 145-150, Gliwice, Poland, 16-18 Jun. 2011.
[8] M. Veshala, R. Jatooth, and K. R. Reddy, "Reduction of short-channel effects in FinFET," International Journal of Engineering and Innovative Technology, IJEIT'13, vol. 2, pp. 118-124, Mar. 2013.
[9] S. Zhu, et al., " N-type Schottky barrier source/drain MOSFET using ytterbium silicide," IEEE Electron Devices Lett, vol. 25, no. 8, pp. 565-567, Aug. 2004.
[10] A. Dutta, K. Koley, S. K. Saha, and C. K. Sarkar, "Effect of source/ drain lateral straggle on distortion and intrinsic performance of asymmetric underlap DG-MOSFET," IEEE Journal of the Electron Devices Society, vol. 2, no. 6, pp. 135-144, Nov. 2014.
[11] C. W. Lee, et al., "Junctionless multi-gate field-effect transistor," Appl. Phys. Lett, Appl. Phys. Lett., vol. 94, no. 5, pp. 053511-1-053511-2, Feb. 2009.
[12] A. Kranti, et al., "Junctionless nanowire transistor (JNT): properties and design guidelines," in Proc. of the European Solid-State Device Research Conf., ESSDERC'10, pp. 357-360, Sevilla, Spain, 14-16 Sept. 2010.
[13] C. W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, et al., "Performance estimation of junctionless multigate transistors," Solid State Electron., vol. 54, no. 2, pp. 97-103, Feb. 2010.
[14] S. Gundapaneni, S. Ganguly, and A. Kottanthar-ayil, "Bulk planar junctionless transistor (BPJL-T): an attractive device alternative for scaling," IEEE Electron Device Lett, vol. 32, no. 3, pp. 261-263, Mar. 2011.
[15] C. W. Lee, et al., "Reduced electric field in junctionless transistors," Appl. Phys. Lett, vol. 96, no. 7, pp. 073510, Feb. 2010.
[16] R. Hosseini, "Analysis and simulation of a junction less double gate MOSFET for high-speed applications," IEEE Trans. on Electron Device, vol. 67, no. 9, pp. 1615-1618, Nov. 2015.
[17] P. Bal, B. Ghosh, P. Mondal, and M. W. Akram, "A laterally graded junctionless transistor," Journal of Semiconductors, vol. 35, no. 3, pp. 034003-4, Mar. 2014.
[18] S. K. Sharma, B. Raj, and M. Khosla, "Performance enhancement of junctionless nanowire FET with laterally graded channel doping and high spacers," in Proc. IEEE 4th Global Conf. on Consumer Electronics, GCCE'15, pp. 556-559, Osaka, Japan, 27-30 Oct. 2015.
[19] J. C. Ho, et al., "Controlled nanoscale doping of semiconductors via molecular monolayers," Nature Mater., vol. 7, pp. 62-67, Jan. 2008.
[20] Y. J. Lee, et al., "Low-temperature microwave annealing processes for future IC fabrication-a review," IEEE Trans. on Electron Devices, vol. 61, no. 3, pp. 651-665, Mar. 2014.
[21] Silvaco Int. ATLAS User's Manual. Device Simulation Software, Silvaco International, Santa Clara, CA, 2015.
[22] M. Vadizadeh, M. Fathipour, and G. Dervish, "Silicon on raised insullator field effect diode (sori-fed) for alleviating scaling problem in fed," International J. of Modern Physics B, vol. 28, no. 5, pp. 1450038-1450053, Feb. 2014.
[23] M. Vadizadeh, "Improving gate delay and ION/IOFF hetrostructure field effect diode (H-FED) by using heavy doped layers in the channel," Applied Physics, vol. 122, no. 4, pp. 460-469, Apr. 2016.