طراحی حلقه قفل فاز با توان مصرفی کم و ثبات بالا درفرکانس 2/45 گیگا هرتز

چکیده مقاله :

در این مقاله، طراحی و شبیه‌سازی حلقه قفل فاز (PLL) با فرکانس مرکزی 45/2 گیگاهرتز ارائه شده است. این PLL با استفاده از تکنولوژی 18_/0 میکرون CMOS و نرم‌افزار HSPICE شبیه‌سازی شده است. ساختار پیشنهادی شامل بلوک‌های اصلی مانند آشکارساز فاز، پمپ بار، فیلتر پایین‌گذر، نوسان‌ساز کنترل‌شده با ولتاژ و تقسیم‌کننده است. مقادیر دقیق پارامترهای مدار از طریق شبیه‌سازی‌های گسترده به دست آمده و برای دستیابی به عملکرد بهینه تنظیم شده‌اند. نتایج شبیه‌سازی نشان می‌دهند که این PLL  با توان مصرفی کمتر از 56/13 میلی‌وات، زمان قفل حدود 16 دوره تناوب فرکانس مرکزی، و نویز فاز dBc/Hz  115 - در فرکانس 1 مگاهرتز عملکردی پایدار و دقیق ارائه می‌دهد. این طراحی به دلیل پایداری بالا و مصرف انرژی کم، برای کاربردهایی مانند مودم‌های ADSL، ارتباطات وای‌فای و دستگاه‌های پرتابل مناسب است.

چکیده انگلیسی :

This paper presents the design and simulation of a phase-locked loop (PLL) with a center frequency of 2.45 GHz, implemented using 0.18 µm CMOS technology and HSPICE simulation tools. The proposed PLL architecture comprises key components including a phase detector, charge pump, low-pass filter, voltage-controlled oscillator, and frequency divider. Circuit parameters were meticulously optimized through extensive simulations to ensure high performance. Results demonstrate stable and precise operation, with a power consumption below 13.56 mW, a lock time of approximately 16 reference cycles, and a phase noise of −115 dBc/Hz at 1 MHz offset. Owing to its low power usage and robust stability, the design is well-suited for applications such as ADSL modems, Wi-Fi communication systems, and portable electronic devices.

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