ارائه یک رویکرد نگاشت در شبکه روی تراشه مبتنی بر الگوریتم جستجوی هارمونی
محورهای موضوعی : مهندسی برق و کامپیوتر
زهرا باقری
1
(دانشگاه آزاد پرند)
فاطمه وردی
2
(دانشگاه آزاد اسلامی واحد پرند)
علیرضا محجوب
3
(دانشگاه آزاد اسلامی واحد کرج)
کلید واژه: شبکه‌های روی تراشه, نگاشت, جستجوی هارمونی, فراابتکاری,
چکیده مقاله :
در پیاده‌سازی مبتنی بر شبکه روی تراشه، نگاشت را می‌توان گامی مهم در اجرای برنامه کاربردی دانست. وظایف یک کاربرد، اغلب در قالب یک گراف هسته نمایش داده می‌شود. هسته‌ها با استفاده از یک بستر ارتباطی و غالباً شبکه روی تراشه، بین خود پیوند برقرار می‌کنند و به این منظور، توسعه‌دهندگان الگوریتم‌های گوناگونی را پیشنهاد داده‌اند. در اغلب موارد به‌دلیل پیچیدگی از روش‌های جستجوی دقیق برای یافتن نگاشت استفاده می‌شود. با این حال این روش‌ها برای شبکه‌های با ابعاد کوچک مناسب هستند. با افزایش ابعاد شبکه، زمان جستجو نیز به‌طور نمایی افزایش می‌یابد. این مقاله از دیدگاه یک رویکرد فراابتکاری با استفاده از روش جستجوی هارمونی به تصمیم‌گیری زمانی برای اتصال هسته‌ها به روترها می‌پردازد. رویکرد ما نوعی بهبودیافته از الگوریتم جستجوی هارمونی را با تمرکز روی کاهش توان مصرفی و تأخیر به کار می‌گیرد. تحلیل پیچیدگی الگوریتم، آشکارکننده راه حل مناسب‌تر در مقایسه با الگوریتم‌های مشابه با توجه به الگوی ترافیکی برنامه کاربردی است. الگوریتم در مقایسه با روش‌های مشابه به 98/39% تأخیر کمتر و 11/61% صرفه‌جویی در توان مصرفی دست می‌یابد.
In network-on-chip implementation, mapping can be considered as an important step in application implementation. The tasks of an application are often represented in the form of a core graph. The cores establish a link between themselves using a communication platform and often the network on the chip. For finding proper mapping for an application, developers have proposed various algorithms. In most cases, due to the complexity, exact search methods are used to find the mapping. However, these methods are suitable for networks with small dimensions. As the size of the network increases, the search time also increases exponentially. This article, from the perspective of a heuristic approach, uses the harmony search method to decide when to connect cores to routers. Our approach uses an improved version of the harmony search algorithm with a focus on reducing power consumption and delay. Algorithm complexity analysis reveals a more appropriate solution compared to similar algorithms with respect to application traffic pattern. Compared to similar methods, the algorithm achieves 39.98% less delay and 61.11% saving in power consumption.
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