Modeling a Proposed Nanoscale SOI-Junctionless for Improvement of Steady-State and Frequency Characteristics
Subject Areas : electrical and computer engineering
1 - فني و مهندسي شرق گيلان
Keywords: Buried oxide, junctionless, silicon-on-insulator, buffer layer,
Abstract :
In this paper in order to improve the electrical performance of nanoscale SOI-junctionless, a targeted modification has been performed. The proposed structure has been aimed to reduce the OFF current and self-heating effect. To reduce the self-heating effect, the buried oxide thickness has been reduced into the half and a part of it has been replaced by a buffer layer. Increase in the thermal conduction and making an extra depletion layer in the buffer layer/channel region interface are led to improvement of the electrical performance in the terms of DC and AC. In the proposed method, which is based on the energy band modification, the parameters such as IOFF, ION/IOFF, subthreshold swing, lattice temperature, voltage gain, transconductance, parasitic capacitances, power gains, cut-off frequency, maximum oscillation frequency and minimum noise figure have been improved. Also, a designing consideration for the role of buffer layer on the proposed device has been performed. Comparing structures under the study simulated by the SILVACO showed the electrical performance superiority for the proposed device.
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