Write Error Rate Reduction Based on Thermal Effect and Dual-Vdd
Subject Areas : electrical and computer engineeringحمیدرضا زرندی 1 * , Sh. Jalilian 2
1 - Amirkabir Univ of Tech
2 -
Keywords: Nonvolatile memorymagnetic tunnel Junction (MTJ)STT-MRAMwrite error rate (WER)process variation (PV),
Abstract :
Write Error (WER) is one of the most drawbacks of STT-MRAM based memories. This problem usually occurred because of thermal instability and process variation. Although some methods have been proposed for WER reduction, they often did not consider the thermal effect of MTJ and had significant overhead. Therefore, proposing a new method in a lower layer of abstraction with the minimum penalty is essential. In this regard, a write driver core has been proposed, which uses two distinct ways according to the state of writing data based on the thermal feature of MTJ cell and by Dual-Vdd method. Simulation results show 11.38% write latency reduction without area and power penalty.
[1] S. Borkar and A. A. Chien, "The future of microprocessors," ACM J. of the Communications, vol. 54, no. 5, p. 67, May 2011.
[2] W. M. Holt, "1.1 Moore's law: a path going forward," in Proc. IEEE Int. Solid-State Circuits Conf., ISSCC'16, pp. 8-13, San Francisco, CA, USA, 31 Jan.-4 Feb. 2016.
[3] S. Rusu, High-Performance Digital-2015 Trends, 2015. [Online]. Available: http://isscc.org/doc/2015/isscc2015_trends.pdf. [Accessed: 14-Jul-2018].
[4] S. Mittal, "A survey of architectural techniques for improving cache power efficiency," Sustainable Computing: Informatics and Systems, vol. 4, no. 1, pp. 33-43, ???. 2014.
[5] F. Hamzaoglu, et al., "A 1 Gb 2 GHz embedded DRAM in 22 nm tri-gate CMOS technology," in Proc. IEEE Int. Solid-State Circuits Conf., ISSCC'14, pp. 230-231, San Francisco, CA, USA, 9-13 Feb. 2014.
[6] V. Sridharan, et al., "Memory errors in modern systems the good, the bad, and the ugly," in Proc. of the 20th Int. Conf. on Architectural Support for Programming Languages and Operating Systems, ASPLOS'15, pp. 297-310, Mar. 2015.
[7] H. S. Philip et al., "Phase change memory," Proceedings of the IEEE, vol. 98, no. 12, pp. 2201-2227, Dec. 2010.
[8] C. Augustine, N. N. Mojumder, X. Fong, S. H. Choday, S. P. Park, and K. Roy, "Spin-transfer torque MRAMs for low power memories: perspective and prospective," IEEE Sensor J., vol. 12, no. 4, pp. 756-766, Apr. 2012.
[9] H. F. Liu, S. S. Ali, and X. F. Han, "Perpendicular magnetic tunnel junction and its application in magnetic random access memory," Chinese Physics, vol. 23, no. 7, p. 77501, Jun. 2014.
[10] H. Akinaga and H. Shima, "Resistive random access memory (ReRAM) based on metal oxides," Proceedings of the IEEE, vol. 98, no. 12, pp. 2237-2251, Dec. 2010.
[11] C. Augustine, et al., "Spin-transfer torque MRAMs for low power memories: perspective and prospective," IEEE Sensor J., vol. 12, no. 4, pp. 756-766, Apr. 2012.
[12] S. Mittal and V. Jeffrey, "Reliability tradeoffs in design of volatile and nonvolatile caches," J. of Circuits, Systems and Computers, vol. 25, no. 11, pp. 1650139:1-1650139:14, Jun. 2016.
[13] P. Chi, S. Li, Y. Cheng, Y. Lu, S. H. Kang, and Y. Xie, "Architecture design with STT-RAM: opportunities and challenges," in Proc. of Asia South Pacific Design Automation Conf., ASP-DAC'16, , pp. 109-114, Macau, China, 25-28 Jan. 2016.
[14] R. Bishnoi, M. Ebrahimi, F. Oboril, and M. B. Tahoori, "Improving write performance for STT-MRAM," IEEE Trans. on Magnetics, vol. 52, no. 8, pp. 1-11, Aug. 2016.
[15] H. Farkhani, M. Tohidi, A. Peiravi, J. K. Madsen, and F. Moradi, "STT-RAM energy reduction using self-referenced differential write termination technique," IEEE Trans. on Very Large Scale Integration Systems, vol. 25, no. 2, pp. 476-487, Feb. 2017.
[16] Y. Zhang, et al., "Compact modeling of perpendicular-anisotropy CoFeB/MgO magnetic tunnel junctions," IEEE Trans. on Electron Devices, vol. 59, no. 3, pp. 819-826, Mar. 2012.
[17] D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, "Cost-efficient self-terminated write driver for spin-transfer-torque RAM and logic," IEEE Trans. on Magnetics, vol. 50, no. 11, pp. 1-4, Nov. 2014.