Observable Optimized Selective Hardening of Combinational Circuits against Soft-Error
Subject Areas : electrical and computer engineeringR. Niaraki Asli 1 * , H. Salemi 2
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Keywords: Soft error combinational circuit observability reliability critical charge,
Abstract :
Due to the shrinking of feature size, reduction in supply voltage and technology scaling, the sensitivity to radiation induced transient faults of digital systems has dramatically increased. Soft error causes transient distortion in circuit operation and is expected to become very important in combinational logic with increment of the circuit frequency. In this paper, we introduce an optimized method for hardening of combinational logic circuits against soft errors. In this method, first we have found the most sensitive nodes of the circuit by observability computations. Next for optimizing power-delay product and area, the reliability of the circuit has been computed and the number of the necessary nodes for hardening will be identified. In the next step, three different hardening methods including time redundancy, Schmitt trigger and transistor feedback have been carried out on standard test circuits as our vehicles. The comparison of three method results show that the hardened circuits with Schmitt trigger have the most cumulative critical charge and the least power-delay product and lead to an optimum hardening. Moreover, the simulation results approve the optimized hardening is obtained from suitable selecting the number of required nodes considering observability concepts and reliability computations together with the best node hardening method. Monte-Carlo simulations also approve the performance of the proposed method against process variations.
[1] P. Mongkolkachit and B. Bhuva, "Design technique for mitigation of alpha-particle-induced single-event transients in combinational logic," IEEE Trans. on Device and Materials Reliability, vol. 3, no. 3, pp. 82-89, Sept.. 2003.
[2] D. B. Limbrick, N. N. Mahatme, W. H. Robinson, and B. L. Bhuva, "Reliability-aware synthesis of combinational logic with minimal performance penalty," IEEE Trans. on Nuclear Science, vol. 60, no. 4, pp. 2776-2781, Aug. 2013.
[3] N. N. Mahatme, et al., "Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies," in Proc. IEEE Int. Reliability Physics Symp., IRPS'10, pp. 1031-1035, Jun. 2010.
[4] N. George and J. Lach, "Characterization of logical masking and error propagation in combinational circuits and effects on system vulnerability," in Proc. Int. Conf. on Dependable Systems & Networks, pp. 323-334, Jun. 2011.
[5] S. Mitra, et al., "Combinational logic soft error correction," in Proc. IEEE Int. Test Conf., 9 pp., Oct. 2006.
[6] C. Lazzari, G. Wirth, F. L. Kastensmidt, L. Anghel, and R. A. Reis, "Asymmetric transistor sizing targeting radiation-hardened circuts," Springer Electrical Engineering J., vol. 94, no. 1, pp. 11-18, Mar. 2012.
[7] K. Bhattacharya and N. Ranganathan, "RADJAM: a novel approach for reduction of soft errors in logic circuits," in Proc. Int. Conf. on VLSI Design, pp. 453-458, Jan. 2009.
[8] Y. Sasaki, K. Namba, and H. Ito, "Circuit and latch capable of masking soft errors with schmitt trigger," Springer Electronic Testing J., vol. 24, no. 1-3, pp. 11-19, Jun. 2008.
[9] R. Niaraki Asli and S. Taghipour, "MOCA ARM: analog reliability measurement based on Monte Carlo analysis," J. of Electrical and Computer Engineering Innovations, vol. 4, no. 1, pp. 9-14, Autmn 2016.
[10] I. Polian and J. Hayes, "Selective hardening: toward cost-effective error tolerance," IEEE Design Test of Computers, vol. 28, no. 3, pp. 54-63, May-Jun. 2011.
[11] S. N. Pagliarini, L. A. Naviner, and J. F. Naviner, "Selective hardening methodology for combinational logic," Latin American Test Workshop, 6 pp., Quito, Ecuador,Apr. 2012.
[12] W. Sootkaneung and K. K. Saluja, "Soft error reduction through gate input dependent weighted sizing in combinational circuits," in Proc. Int. Symp. on Quality Electronic Design, ISQED'11, pp. 603-610, Mar. 2011.
[13] Z. Navabi, Digital System Test and Testable Design, Springer Science, New York, 2011.
[14] Benchmarksat, http://web.eecs.umich.edu/~jhayes/iscas.restore/benchmark.html
[15] D. T. Franco, M. C. Vasconcelos, L. Naviner, and J. F. Naviner, "Signal probability for reliability evaluation of logic circuits," Microelectronics Reliability, vol. 48, no. 8-9, pp. 1586-1591, Aug.-Sept. 2008.
[16] G. C. Messenger, "Collection of charge on junction nodes from ion tracks," IEEE Trans. on Nuclear Science, vol. 29, no. 6, pp. 2024-2031, Dec. 1982.