Design and Implementation of Two Pipeline Architectures for Computing High-Order Moments of Grey-Level Images
Subject Areas : electrical and computer engineering
M. Monajati
1
*
,
E. Kabir
2
,
3
1 -
2 - Tarbiat Modares University
3 -
Keywords: Momentparallel processingpipeline architecturesreal time processsystolic array,
Abstract :
Moments are utilized in image processing for pattern recognition, machine vision and numerous feature extraction techniques. Due to computational complexity, it is difficult to use high order moments in real time processing. This paper presents the design of two new architectures for real time computation of moments, up to order 14, M00 to M77, in gray level images, based on parallel systolic arrays and pipelining technique, using a 0.18μm CMOS technology. Implementation of the moment processing element (MPE) of the first architecture illustrates a processing speed of 125 frames/s for 1024×1024 grey-level images. The maximum operating frequency and the power consumption for an architecture with 5 elements is 133 MHz and 14.36 mW, respectively. Since the design is very low power, the number of parallel MPE’s can be easily increased. Simulation shows that with 11 parallel MPE’s, the first 49 moments of 1024×1024 image are computed with the speed of 30 frames/sec. To further decrease the latency of the first architecture, the second architecture is proposed, in which the add operation is performed only with a single adder and a compressor. Simulation shows that the latency of the second architecture is 3.3 times lower than that of the first architecture. Implementation of the second architecture illustrates the maximum operating frequency and the power consumption of 125 MHz and 58.34 mW, respectively. Operating frequency and power consumption of the second architecture is approximately the same as that of the first architecture which befit real time applications.
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