طراحی ضرب‌کننده‌های ممیز- شناور با قابلیت کار در مدهای عادی و تحمل‌پذیر اِشکال با استفاده از کاهش دقت محاسبات
محورهای موضوعی : مهندسی برق و کامپیوترمریم مهاجر 1 , مجتبی ولی‌نتاج 2 *
1 - دانشگاه صنعتی نوشیروانی بابل
2 - مهندسی برق و کامپیوتر
کلید واژه: دقت کاهش‌یافتهتحمل‌پذیری اشکالتشخیص خطاتصحیح خطاضرب‌کننده ممیز- شناور,
چکیده مقاله :
عملیات ضرب یکی از مهم‌ترین محاسبات مورد استفاده در انواع پردازش‌های سیگنال خصوصاً صوت و تصویر محسوب می‌شود. با این حال، ضرب‌کننده‌ها به عنوان مدارهای دیجیتالی به خاطر وجود عوامل محیطی گوناگون مانند انواع نویزها مستعد تولید خروجی‌های نادرست هستند. در این مقاله، روشی جدید برای طراحی ضرب‌کننده ممیز- شناور 32بیتی ارائه می‌شود که می‌تواند با توجه به شرایط محیطی که در آن استفاده می‌شود، در دو مد کاری عادی یا تحمل‌پذیر اشکال عمل کند. در مد تحمل‌پذیر اشکال، با کاهش دقت محاسبات و قبول مقدار ناچیزی خطای محاسباتی در خروجی، بخشی از مدار اولیه آزاد شده و برای فراهم‌کردن محاسبات افزونه به منظور تشخیص یا تصحیح خطاهای ناشی از اشکال‌ها استفاده می‌شود. بدین روش، دو معماری ضرب‌کننده با قابلیت تشخیص یا تصحیح خطا پیشنهاد می‌شوند که در مد کاری تحمل‌پذیر اشکال، دارای قابلیت اطمینان مناسبی در برابر انواع اشکال‌های دائمی و گذرا هستند. نتایج پیاده‌سازی نشان می‌دهد که در مد تحمل‌پذیر اشکال به جای 23 بیت مانتیس اولیه، حفظ 13 بیت برای دست‌یافتن به ضرب‌کننده با قابلیت تشخیص خطا و حفظ 11 بیت برای دست‌یافتن به ضرب‌کننده با قابلیت تصحیح خطا، با سربار مساحت و توان قابل قبول که از 12% تا 26% خواهد بود و همچنین حفظ دقت مورد نیاز برای اکثر کاربردها، مناسب است.
Multiplication is one of the important computations required for different signal processing applications especially regarding voice and image. However, the multipliers as digital circuits are susceptible to different environmental effects such as noises. In this paper, a new approach is proposed for designing a 32-bit floating-point multiplier which can operate in two operational modes, normal and fault-tolerant, dependent to the environmental conditions. In the fault-tolerant mode, by reducing the normal precision and accepting a negligible error in the output, a portion of preliminary circuit is released which is used for redundant computations in order to detect or correct errors. This way, two multiplier architectures with error detection or correction capability are proposed that have a beneficial reliability against different types of permanent and transient faults. The implementation results show that in the fault-tolerant mode, maintaining 13 bits instead of 23 bits for the mantissa will be enough to achieve an error detecting multiplier, and maintaining 11 bits will be enough to achieve an error correcting multiplier with acceptable area and power overheads (from 12% to 26%) while their precisions are enough for most applications.
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