﻿<?xml version="1.0" encoding="utf-8"?><records><record><language>per</language><publisher>  Iranian Research Institute for Electrical Engineering</publisher><journalTitle>فصلنامه مهندسی برق و مهندسی کامپيوتر ايران</journalTitle><issn>16823745</issn><eissn>16823745</eissn><publicationDate>2025-12</publicationDate><volume>23</volume><issue>2</issue><startPage>81</startPage><endPage>94</endPage><documentType>article</documentType><title language="eng">A Comprehensive Review of the Synthesis of Linear and Planar Antenna Arrays</title><authors><author><name>A. Pesarakloo</name><email>ali.pesarakloo68@gmail.com</email><affiliationId>1</affiliationId></author><author><name>M. Khalaj-Amirhosseini</name><email>khalaja@iust.ac.ir</email><affiliationId>2</affiliationId></author></authors><affiliationsList><affiliationName affiliationId="1">Faculty of Elec. and Comp. Eng., Babol Noshirvani University of Technology, Babol, Iran</affiliationName><affiliationName affiliationId="2">Dept. of Elec. Eng., Iran University of Science and Technology, Tehran. Iran</affiliationName></affiliationsList><abstract language="eng">&lt;p style="margin: 0cm; margin-bottom: .0001pt; text-align: justify;"&gt;An antenna array is created by assembling a set of radiating elements in a specific geometric structure, enabling unique features that conventional antennas cannot achieve. These features include the ability to scan radiation patterns, patterns with high directivity, and patterns with arbitrary shapes. Three general strategies are used for designing antenna arrays: determining excitation current amplitudes, excitation current phases, and the distance between elements. Various pattern synthesis methods have been proposed for each of these strategies.&lt;/p&gt;
&lt;p style="margin: 0cm; margin-bottom: .0001pt; text-align: justify;"&gt;In the synthesis of broadside radiation patterns, traditional methods focus on determining the excitation amplitude of elements. These methods include uniform excitation for maximum directivity and Chebyshev and Taylor excitation for minimizing the Side Lobe Level (SLL) for a specific Half-Power Beam Width (HPBW). Recently, new analytical synthesis methods have been introduced to achieve broadside patterns with maximum directivity, SLL, or HPBW control. The first part of this process, concentrating on determining the excitation amplitude strategy, explains these methods and compares them to traditional Chebyshev and uniform excitation methods.&lt;/p&gt;
&lt;p style="margin: 0cm; margin-bottom: .0001pt; text-align: justify;"&gt;To generate patterns with arbitrary and asymmetric shapes, the conventional approach involves determining both the excitation amplitude and phase of elements. However, implementing such excitation is intricate and costly. Recent articles have presented methods for synthesizing asymmetric patterns by solely determining the excitation phase of elements. In the second part, these methods are scrutinized along with their strengths and weaknesses.&lt;/p&gt;
&lt;p style="margin-top: 0cm; text-align: justify;"&gt;A novel method has recently emerged for synthesizing broadside patterns with a specified Side Lobe Level. Instead of adjusting the excitation amplitude of elements, this method focuses on the distance between elements. These arrays, termed non-uniformly spaced arrays, are known for their straightforward implementation. The third part explores the synthesis methods of these arrays, comparing them to uniformly spaced arrays and outlining their advantages and disadvantages.&lt;/p&gt;</abstract><fullTextUrl>http://ijece.org/Article/51487</fullTextUrl><keywords><keyword>Antenna array</keyword><keyword> radiation pattern synthesis</keyword><keyword> uniformly spaced array</keyword><keyword> non-uniformly spaced array</keyword></keywords></record><record><language>per</language><publisher>  Iranian Research Institute for Electrical Engineering</publisher><journalTitle>فصلنامه مهندسی برق و مهندسی کامپيوتر ايران</journalTitle><issn>16823745</issn><eissn>16823745</eissn><publicationDate>2025-12</publicationDate><volume>23</volume><issue>2</issue><startPage>95</startPage><endPage>106</endPage><documentType>article</documentType><title language="eng">Performance Analysis of Different Control Methods in Permanent Magnet Synchronous Motor Drives: A Comparative Study</title><authors><author><name>M. Salmanfar</name><email>m_salmanfar@mut.ac.ir</email><affiliationId>1</affiliationId></author><author><name>A. Dehestani Kolagar</name><email>a_dehestani@mut.ac.ir</email><affiliationId>2</affiliationId></author><author><name>Mohammad Reza  Alizadeh Pahlavani</name><email>mr_alizadehp@mut.ac.ir</email><affiliationId>3</affiliationId></author><author><name>Yousef  Koohmaska</name><email>koohmaskan@chmail.ir</email><affiliationId>4</affiliationId></author></authors><affiliationsList><affiliationName affiliationId="1">Faculty of Elec. and Com. Eng., Malek Ashtar University of Technology, Tehran, Iran</affiliationName><affiliationName affiliationId="2">Faculty of Elec. and Com. Eng., Malek Ashtar University of Technology, Tehran, Iran</affiliationName><affiliationName affiliationId="3">Faculty of Elec. and Com. Eng., Malek Ashtar University of Technology, Tehran, Iran</affiliationName><affiliationName affiliationId="4">Faculty of Elec. and Com. Eng., Malek Ashtar University of Technology, Tehran, Iran</affiliationName></affiliationsList><abstract language="eng">&lt;p&gt;PMSM motors are suitable for applications that require precise measurement of torque, speed, or position, and because of their characteristics, they are used in military, industrial, and automation systems, and they can be a suitable alternative to traditional induction motors. Classical controllers are widely used in controlling the speed of permanent magnet synchronous motors; But these controllers do not perform well due to the non-linear characteristics of the motor or in the presence of disturbances and load changes. The model predictive control method can optimize the future control path to achieve the desired dynamic efficiency. In this paper, the performance of the model predictive control (MPC) method is compared with vector control (FOC), direct torque control (DTC), hysteresis control, and classical PWM-based linear control. Also, due to the importance of the issue of losses, comparative studies of switching losses are conducted between different control methods and model predictive control method in three-phase two-level voltage source inverters. The results obtained show that the model predictive control method effectively controls the load current and has a much better performance compared to the classical methods. Finally, the simulation results are compared and analyzed.&lt;/p&gt;</abstract><fullTextUrl>http://ijece.org/Article/49594</fullTextUrl><keywords><keyword>Permanent magnet synchronous motor</keyword><keyword> model predictive control</keyword><keyword> switching losses.</keyword></keywords></record><record><language>per</language><publisher>  Iranian Research Institute for Electrical Engineering</publisher><journalTitle>فصلنامه مهندسی برق و مهندسی کامپيوتر ايران</journalTitle><issn>16823745</issn><eissn>16823745</eissn><publicationDate>2025-12</publicationDate><volume>23</volume><issue>2</issue><startPage>107</startPage><endPage>116</endPage><documentType>article</documentType><title language="eng">Design of a Power Electronic Transformer Structure Based on Multi-Port Converters with Integrated Energy Storage Capability</title><authors><author><name>H. Kavosh</name><email>hamidkavosh96@gmail.com</email><affiliationId>1</affiliationId></author><author><name>M. Saradarzadeh</name><email>saradar@jsu.ac.ir</email><affiliationId>2</affiliationId></author></authors><affiliationsList><affiliationName affiliationId="1">Depف.of Elec. and Comp. Eng., Jundi-Shapur University of Technology, Dezful, Iran.</affiliationName><affiliationName affiliationId="2">Depف.of Elec. and Comp. Eng., Jundi-Shapur University of Technology, Dezful, Iran.</affiliationName></affiliationsList><abstract language="eng">&lt;p style="direction: ltr;"&gt;Power Electronic Transformers (PETs) have emerged as promising alternatives to conventional Line Frequency Transformers (LFTs) in modern power systems. For high-power and high-voltage applications, modular configurations such as Cascaded H-Bridge (CHB) structures are widely recognized as effective PET design solutions. However, existing PET topologies, most commonly based on Dual Active Bridge (DAB) converters, suffer from significant drawbacks, including low-frequency distortion power in DC-link capacitors and degraded performance under fault conditions.&lt;/p&gt;
&lt;p style="direction: ltr;"&gt;To overcome these limitations, this paper introduces several multi-port converter-based PET architectures. By employing multiple five-port active bridge converters in conjunction with supercapacitors and an advanced control strategy for inter-port power management, the proposed PET achieves enhanced dynamic performance and fault-tolerant operation at both medium-voltage (MV) and low-voltage (LV) levels. Conceptual design and comprehensive simulation studies conducted in Matlab/Simulink confirm the effectiveness and robustness of the proposed topologies.&lt;/p&gt;</abstract><fullTextUrl>http://ijece.org/Article/49084</fullTextUrl><keywords><keyword>Multi-active bridge</keyword><keyword> power electronics transformer</keyword><keyword> energy storage</keyword><keyword> single phase shift.</keyword></keywords></record><record><language>per</language><publisher>  Iranian Research Institute for Electrical Engineering</publisher><journalTitle>فصلنامه مهندسی برق و مهندسی کامپيوتر ايران</journalTitle><issn>16823745</issn><eissn>16823745</eissn><publicationDate>2025-12</publicationDate><volume>23</volume><issue>2</issue><startPage>117</startPage><endPage>126</endPage><documentType>article</documentType><title language="eng">Modeling Transient Time-Dependent Behavior of a Digital Phase-Locked Loop Circuit Using Gated Recurrent Neural Network </title><authors><author><name>S. F. Mousavi</name><email>f.mousavi@stu.yazd.ac.ir</email><affiliationId>1</affiliationId></author><author><name>S. A. Sadrossadat</name><email>alireza.sadr@yazd.ac.ir</email><affiliationId>2</affiliationId></author><author><name>A. Moftakharzadeh</name><email>ali.moftakharzadeh@gmail.com</email><affiliationId>3</affiliationId></author></authors><affiliationsList><affiliationName affiliationId="1">Dept. of Elec. Eng., Yazd University, Yazd, Iran</affiliationName><affiliationName affiliationId="2">Dept. of Comp. Eng., Yazd University, Yazd, Iran</affiliationName><affiliationName affiliationId="3">Dept. of Elec. Eng., Yazd University, Yazd, Iran</affiliationName></affiliationsList><abstract language="eng">&lt;p class="MsoNormal" style="direction: ltr;"&gt;&lt;span style="font-size: 12.0pt; mso-bidi-font-size: 14.0pt; line-height: 107%; font-family: 'Times New Roman',serif; mso-bidi-font-family: 'B Nazanin';"&gt;Nowadays, neural networks are a powerful tool for modeling complex and nonlinear circuits. In this paper, the transient time-dependent behavior of a digital phase-locked loop circuit is modeled using two time-dependent neural network models. Modeling with an RNN (Recurrent Neural Network) faces the challenge of gradient vanishing during the training phase and does not perform well in terms of speed and accuracy. To achieve desirable training and testing error values, the GRU (Gated Recurrent Unit) neural network is used for modeling. This network, due to the presence of update and reset gates, can overcome the gradient vanishing problem and provide acceptable modeling results. A comparison of the results of these two networks shows that the method based on the gated neural network structure has superior capability and performance in modeling the behavior of nonlinear circuits.&lt;/span&gt;&lt;/p&gt;</abstract><fullTextUrl>http://ijece.org/Article/48062</fullTextUrl><keywords><keyword>DPLL circuit</keyword><keyword> nonlinear circuit dynamic response modeling</keyword><keyword> gradient vanishing</keyword><keyword> GRU neural network</keyword></keywords></record><record><language>per</language><publisher>  Iranian Research Institute for Electrical Engineering</publisher><journalTitle>فصلنامه مهندسی برق و مهندسی کامپيوتر ايران</journalTitle><issn>16823745</issn><eissn>16823745</eissn><publicationDate>2025-12</publicationDate><volume>23</volume><issue>2</issue><startPage>127</startPage><endPage>137</endPage><documentType>article</documentType><title language="eng">Enhanced Automatic Test Pattern Generation Using PSO-FAN Algorithm</title><authors><author><name>S. H. Zahiri</name><email>hzahiri@birjand.ac.ir</email><affiliationId>1</affiliationId></author><author><name>Ehsan Haghparast</name><email>ehsan.haghparast66@gmail.com</email><affiliationId>2</affiliationId></author><author><name>Abolfazl Bijari</name><email>a.bijari@birjand.ac.ir</email><affiliationId>3</affiliationId></author></authors><affiliationsList><affiliationName affiliationId="1">University of Birjand</affiliationName><affiliationName affiliationId="2">Department of Electronics Engineering, University of Birjand, Birjand, Iran</affiliationName><affiliationName affiliationId="3">Department of Electronics Engineering, University of Birjand, Birjand, Iran</affiliationName></affiliationsList><abstract language="eng">&lt;p style="text-align: left;"&gt;The domain of Very Large Scale Integrated (VLSI) circuit testing has experienced advancements in methodologies for fault detection, which are crucial for addressing the complexities of modern applications. Traditional testing techniques frequently fall short in achieving precise fault localization, highlighting the necessity for the development of enhanced methodologies. This paper endeavors to investigate the implementation of an optimized test generation algorithm aimed at improving testing efficiency and increasing fault coverage. In this study, we utilized a (PSO)-enhanced FAN (fan-out-oriented algorithm) applied to ISCAS'89 benchmark circuits. The optimization process involved refining the decision trees utilized in the FAN algorithm through a rigorously defined cost function, which strikes a balance between accuracy, complexity, and operational efficiency. The results indicate improvement in both fault coverage and detection efficiency. Furthermore, the optimization process resulted in a reduction of required test vectors, thereby enhancing testing efficiency, particularly in high-volume production environments. The study also introduces the development of diagnostic metrics that provide deeper insights into circuit failures and proposes design-for-testability techniques to improve reliability. The integration of PSO within the FAN algorithm not only facilitates the generation of robust test solutions but also produces high-quality test vectors.&lt;/p&gt;</abstract><fullTextUrl>http://ijece.org/Article/49064</fullTextUrl><keywords><keyword>Fault Detection</keyword><keyword> ATPG</keyword><keyword> Optimization</keyword><keyword> VLSI Circuits</keyword><keyword> Heuristic Algorithms</keyword><keyword> FAN Algorithm</keyword></keywords></record><record><language>per</language><publisher>  Iranian Research Institute for Electrical Engineering</publisher><journalTitle>فصلنامه مهندسی برق و مهندسی کامپيوتر ايران</journalTitle><issn>16823745</issn><eissn>16823745</eissn><publicationDate>2025-12</publicationDate><volume>23</volume><issue>2</issue><startPage>138</startPage><endPage>144</endPage><documentType>article</documentType><title language="eng">A New Active Impedance Source Inverter with Reduced Voltage Stress Across the Switches</title><authors><author><name>V. Ranjbarizad</name><email>vidaranjbarizad2@gmail.com</email><affiliationId>1</affiliationId></author><author><name>E. Babaei</name><email>e-babaei@tabrizu.ac.ir</email><affiliationId>2</affiliationId></author></authors><affiliationsList><affiliationName affiliationId="1">Faculty of Elec. and Comp. Eng., University of Tabriz, Tabriz, Iran</affiliationName><affiliationName affiliationId="2">Faculty of Elec. and Comp. Eng., University of Tabriz, Tabriz, Iran</affiliationName></affiliationsList><abstract language="eng">&lt;p style="direction: ltr;"&gt;In this paper, a new active impedance source inverter with low voltage stress across the elements and suitable voltage gain is proposed. This feature of the proposed inverter reduces the size, volume and cost of the structure. The proposed inverter consists of two parts: an impedance source on the input side and an H-bridge on the output side, which generates a three-level output voltage. An analysis of the operating modes and the control method applied to generate the gate pulses of the switches is presented, and the voltage gain of the proposed structure is calculated. In addition, the active and passive components of the proposed structure are designed. In the following, a comparative analysis is provided from the points of view of voltage gain, voltage stress across the switches, diodes and also the total voltage of the capacitors, along with a comparative diagram of the number of elements, between the proposed structure and several conventional impedance source structures. Finally, the proposed structure is designed in the PSCAD environment, and its results are fully analyzed, which shows the proper performance of the proposed structure and the accuracy of the obtained equations.&lt;/p&gt;</abstract><fullTextUrl>http://ijece.org/Article/49099</fullTextUrl><keywords><keyword>Active impedance source inverter</keyword><keyword> Z-source inverter</keyword><keyword> voltage gain</keyword><keyword> voltage stress.</keyword></keywords></record></records>