ﺳﻨﺘﺰ ﺳﻄﺢ ﺑﺎﻻي ﻣﺪارﻫﺎي ﺣﺴﺎﺑﯽ دﻫﺪﻫﯽ ﺑﺮ روي ﻣﻌﻤﺎريﻫﺎي ﻗﺎﺑﻞ ﺑﺎزﭘﯿﮑﺮﺑﻨﺪي درﺷﺖداﻧﻪ
محورهای موضوعی : مهندسی برق و کامپیوتر
1 - دانشگاه سمنان
کلید واژه: ﺳﻨﺘﺰ ﺳﻄﺢ ﺑﺎﻻ, ﺣﺴﺎب دﻫﺪﻫﯽ, ﻣﻌﻤﺎريﻫﺎي ﻗﺎﺑﻞ ﺑﺎزﭘﯿﮑﺮﺑﻨﺪي درﺷﺖداﻧﻪ, نگاشت روی سخت‌افزار, اختصاص منابع,
چکیده مقاله :
اﻓﺰاﯾﺶ ﻗﺎﺑﻠﯿﺖﻫﺎي ﻣﺪارﻫﺎي ﻣﺠﺘﻤﻊ و ﭘﯿﭽﯿﺪﮔﯽ ﺑﺮﻧﺎﻣﻪﻫﺎي ﮐﺎرﺑﺮدي، روشﻫﺎ و اﺑﺰارﻫﺎي ﻃﺮاﺣﯽ ﺳﺨﺖاﻓﺰار را ﺑﻪ ﺳﻤﺖ ﺳﻄﻮح ﺑﺎﻻﺗﺮي از اﻧﺘﺰاع ﺳﻮق داده و ﺳﻨﺘﺰ ﺳﻄﺢ ﺑﺎﻻ، ﯾﮑﯽ از ﮐﻠﯿﺪيﺗﺮﯾﻦ ﮔﺎمﻫﺎ در اﻓﺰاﯾﺶ ﺳﻄﺢ اﻧﺘﺰاع می‌باشد. در ﺳﺎل‌های اﺧﯿﺮ، ﺗﺤﻘﯿﻘﺎت ﮔﺴﺘﺮده‌اي ﺑﺮاي ﻃﺮاﺣﯽ ﺳﺎﺧﺘﺎرﻫﺎي ﻗﺎﺑﻞ ﺑﺎزﭘﯿﮑﺮﺑﻨﺪي ﺑﺎ ﻫﺪف ﺣﺴﺎب دﻫﺪﻫﯽ ﺻﻮرت ﮔﺮﻓﺘﻪ اﺳﺖ. از آنجا که از یک سو، اﺳﺘﻔﺎده ﻣؤﺛﺮ از اﯾﻦ ﺳﺎﺧﺘﺎرﻫﺎ وابسته ﺑﻪ وﺟﻮد اﻟﮕﻮریتم‌ها و اﺑﺰارﻫﺎي ﻣﻨﺎﺳﺐ ﺟﻬﺖ ﭘﯿﺎدهﺳﺎزي ﻃﺮاﺣﯽ ﺑﺮ روي ﺳﺨﺖاﻓﺰار بوده و از سوی دیگر، ﭘﮋوﻫﺶ در زﻣﯿﻨﻪ ﺗﻮﺳﻌﻪ اﯾﻦ دﺳﺘﻪ از اﻟﮕﻮرﯾﺘﻢﻫﺎ بسیار اندک و محدود بوده است، در این مقاله روش‌هایی ﺑﺮاي ﺳﻨﺘﺰ ﺧﻮدﮐﺎر ﺗﻮﺻﯿﻒ ﺳﻄﺢ ﺑﺎﻻ از ﻣﺪارﻫﺎي ﺣﺴﺎﺑﯽ دﻫﺪﻫﯽ بر روي ﯾﮏ ﻣﻌﻤﺎري ﻗﺎﺑﻞ ﺑﺎزﭘﯿﮑﺮﺑﻨﺪي درﺷﺖداﻧﻪ اراﺋﻪ خواهد شد. بستر سخت‌افزاری انتخاب‌شده، معماری قابل بازپیکربندی درشت‌دانه DARA بوده و روش‌های پیشنهادشده برای اختصاص منابع در جریان سنتز، شامل دو الگوریتم مکاشفه‌ای و ILP می‌باشند. نتایج به دست آمده نشان می‌دهند که مطابق انتظار، برای ابعاد محدود معماری مورد استفاده، الگوریتم ILP به میزان قابل توجهی (حدود 30%) بهتر از الگوریتم مکاشفه‌ای عمل می‌نماید.
The increasing capabilities of integrated circuits and the complexity of applications have led hardware design methods and tools to higher levels of abstraction and high-level synthesis is one of the key steps in increasing the level of abstraction. In recent years, extensive research has been conducted on the design of decimal arithmetic reconfigurable architectures. Since, on the one hand, the effective use of these architectures depends on the existence of appropriate algorithms and tools to implement the design on the hardware, and on the other hand, research on the development of these algorithms has been very limited, this paper will present methods for the automated synthesis of decimal arithmetic circuits on a coarse-grained reconfigurable architecture. The platform chosen to execute the proposed algorithms is the DARA coarse-grained reconfigurable architecture, which is optimized for decimal arithmetic. The algorithms proposed for resource allocation of synthesis include a heuristic method and an ILP algorithm. The results show that, as expected, for the limited architectural dimensions used, the ILP algorithm performs significantly (about 30%) better than the heuristic algorithm.
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