بررسی تأثیر سلسله‌مراتب حافظه نهان ناهمگن در پردازنده‌های مراکز داده
محورهای موضوعی : مهندسی برق و کامپیوترعدنان نصری 1 , محمود فتحی 2 * , علی برومندنیا 3
1 - دانشگاه آزاد اسلامی واحد علوم و تحقیقات تهران
2 - دانشگاه علم و صنعت ایران
3 - دانشگاه آزاد اسلامی واحد تهران جنوب
کلید واژه: مرکز داده ابریپردازندهسلسله‌مراتب حافظه نهانحافظه غیر فرارمحک CloudSuite,
چکیده مقاله :
این مقاله به مسأله تأثیر استفاده از حافظه‌های غیر فرار در سلسله‌مراتب حافظه نهان برای پردازنده‌های مراکز داده در عصر سیلیکون تاریک پرداخته است. همان طور که مصرف انرژی به یکی از مباحث مهم عملیات و نگهداری مراکز داده ابری تبدیل شده است، فراهم‌کنندگان سرویس‌های ابری به شدت در این زمینه نگران شده‌اند. تکنولوژی حافظه‌های غیر فرار نوظهور جایگزینی مناسب برای حافظه‌های متداول امروزی می‌باشند. ما در این مقاله از حافظه غیر فرار STT-RAM در مقایسه با حافظه SRAM به عنوان حافظه نهان سطح آخر استفاده می‌کنیم. تراکم بالا، دسترسی خواندن سریع، توان مصرفی نشتی نزدیک به صفر و غیر فرار بودن باعث می‌شود حافظه STT-RAM یک فناوری مهم برای حافظه‌های درون تراشه باشد. در اکثر تحقیقات قبلی که از حافظه‌های غیر فرار بهره گرفته‌اند، روش‌های خاص و مبتنی بر محک‌های متعارف بررسی شده و در مورد محک‌های ابری نوظهور تحت عنوان بارهای کاری Scale-out تحلیل کاملی انجام نداده‌اند. ما در این مقاله با اجرای بارهای کاری Scale-out، تأثیر استفاده از حافظه‌های غیر فرار در سلسله‌مراتب حافظه نهان پردازنده‌های ابری مراکز داده را بررسی می‌کنیم. نتایج آزمایش روی محکِ CloudSuite نشان می‌دهد که استفاده از حافظه STT-RAM در مقایسه با حافظه SRAM در حافظه نهان سطح آخر، میزان انرژی مصرفی را حداکثر 59% کاهش می‌دهد.
This paper focuses on the effect of heterogeneous cache hierarchy in data center processors in the dark silicon era. For extreme-scale high performance computing systems, system-wide power consumption has been identified as one of the key constraints. As energy consumption becomes a key issue for operation and maintenance of cloud data centers, cloud computing providers are becoming significantly concerned. Emerging non-volatile memory technologies are favorable replacement for conventional memory. Here, we employ a nonvolatile memory called spin-transfer torque random access memory (STT-RAM) as an on-chip L2 cache to obtain lower energy compared to conventional L2 caches, like SRAM. High density, fast read access, near-zero leakage power and non-volatility make STT-RAM a significant technology for on-chip memories. In order to decrease memory energy consumption, it is required to address both the leakage and dynamic energy. Previous studies have mainly studied specific schemes based on common applications and do not provide a thorough analysis of emerging scale-out applications with multiple design options. Here, we discuss different outlooks consisting of performance and energy efficiency in cloud processors by running CloudSuite benchmarks as one of scale-out workloads. Experiment results on the CloudSuite benchmarks show that using STT-RAM memory compare to SRAM memory as last level cache, consumes less energy in L2 cache, around 59% at maximum.
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