Mendeley TY _ JOUR ID - 13980131178801 TI - Enhancing Speed, Area and Power Consumption of Carry Select Adders Using a New Grouping Structure JO - Nashriyyah -i Muhandisi -i Barq va Muhandisi -i Kampyutar -i Iran JA - ES LA - fa SN - 16823745 AU - Mohammad Nezhad A. AU - Valinataj Mojtaba AD - دانشگاه صنعتی نوشیروانی بابل AD - دانشکده مهندسی برق و کامپیوتر، دانشگاه صنعتی نوشیروانی بابل Y1 - 2019 PY - 2019 VL - 4 IS - SP - 310 EP - 318 KW - Carry select adderbasic groupingsadder delaypower consumption DO - N2 - Design of low-cost and high-speed datapath is very important for current computing systems. The adders are the essential parts of datapaths in computing systems. Among different types of adders, the carry select adder (CSeA) has a high speed while having the area overhead, as well. A factor influencing the speed of this adder is the incorporated grouping structure dependent to its components' delay. In this paper, at first, the delay and area of different existing CSeA architectures are reduced by utilizing a fast and small multiplexer. Then, a new grouping structure is proposed for more delay reduction based on a delay analysis. Implementation and experimental results show that applying the proposed grouping and modifications on different CSeA architectures leads to a high delay reduction in the add operation compared to the best existing grouping structure. For example, the amount of delay reduction in the investigated 32-bit CSeA architectures is more than 33%. In addition, the average reduction of power-delay-product criterion for 32-bit and 64-bit CSeAs utilizing the proposed grouping equals45% and 35%, respectively, compared to the CSeAs incorporating the current best grouping. UR - rimag.ir/en/Article/28434 L1 - rimag.ir/en/Article/Download/28434 ER -